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EDBA164B4PR-1DITF-R 数据表(PDF) 105 Page - Micron Technology |
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EDBA164B4PR-1DITF-R 数据表(HTML) 105 Page - Micron Technology |
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105 / 152 page  Table 64: IDD Specification Parameters and Operating Conditions (Continued) Notes 1–3 apply to all parameters and conditions Parameter/Condition Symbol Power Supply Notes Idle non-power-down standby current with clock stopped: CK_t = LOW; CK_c = HIGH; CKE is HIGH; CS_n is HIGH; All banks are idle; CA bus inputs are stable; Data bus inputs are stable IDD2NS1 VDD1 IDD2NS2 VDD2 IDD2NS,in VDDQ 4 Active power-down standby current: tCK = tCKmin; CKE is LOW; CS_n is HIGH; One bank is active; CA bus inputs are switching; Data bus inputs are stable IDD3P1 VDD1 IDD3P2 VDD2 IDD3P,in VDDQ 4 Active power-down standby current with clock stop: CK_t = LOW, CK_c = HIGH; CKE is LOW; CS_n is HIGH; One bank is active; CA bus inputs are sta- ble; Data bus inputs are stable IDD3PS1 VDD1 IDD3PS2 VDD2 IDD3PS,in VDDQ 4 Active non-power-down standby current: tCK = tCKmin; CKE is HIGH; CS_n is HIGH; One bank is active; CA bus inputs are switching; Data bus inputs are stable IDD3N1 VDD1 IDD3N2 VDD2 IDD3N,in VDDQ 4 Active non-power-down standby current with clock stopped: CK_t = LOW, CK_c = HIGH CKE is HIGH; CS_n is HIGH; One bank is active; CA bus in- puts are stable; Data bus inputs are stable IDD3NS1 VDD1 IDD3NS2 VDD2 IDD3NS,in VDDQ 4 Operating burst READ current: tCK = tCKmin; CS_n is HIGH between valid commands; One bank is active; BL = 4; RL = RL (MIN); CA bus inputs are switching; 50% data change each burst transfer IDD4R1 VDD1 IDD4R2 VDD2 Operating burst WRITE current: tCK = tCKmin; CS_n is HIGH between valid commands; One bank is active; BL = 4; WL = WLmin; CA bus inputs are switch- ing; 50% data change each burst transfer IDD4W1 VDD1 IDD4W2 VDD2 IDD4W,in VDDQ 4 All-bank REFRESH burst current: tCK = tCKmin; CKE is HIGH between valid commands; tRC = tRFCabmin; Burst refresh; CA bus inputs are switching; Data bus inputs are stable IDD51 VDD1 IDD52 VDD2 IDD5IN VDDQ 4 All-bank REFRESH average current: tCK = tCKmin; CKE is HIGH between valid commands; tRC = tREFI; CA bus inputs are switching; Data bus inputs are stable IDD5AB1 VDD1 IDD5AB2 VDD2 IDD5AB,in VDDQ 4 Per-bank REFRESH average current: tCK = tCKmin; CKE is HIGH between valid commands; tRC = tREFI/8; CA bus inputs are switching; Data bus inputs are stable IDD5PB1 VDD1 5 IDD5PB2 VDD2 5 IDD5PB,in VDDQ 4, 5 Self refresh current (–30˚C to +85˚C): CK_t = LOW, CK_c = HIGH; CKE is LOW; CA bus inputs are stable; Data bus inputs are stable; Maximum 1x self refresh rate IDD61 VDD1 6 IDD62 VDD2 6 IDD6IN VDDQ 4, 6 Self refresh current (+85˚C to +105˚C): CK_t = LOW, CK_c = HIGH; CKE is LOW; CA bus inputs are stable; Data bus inputs are stable IDD6ET1 VDD1 6, 7 IDD6ET2 VDD2 6, 7 IDD6ET,in VDDQ 4, 6, 7 216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM Electrical Specifications – IDD Specifications and Conditions 09005aef85eb530a 216b_220b_2ch_2e0e_embedded_lpddr2.pdf – Rev. F 08 /16 EN 105 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved. |
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