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VSC8540RT 数据表(PDF) 18 Page - Microchip Technology |
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VSC8540RT 数据表(HTML) 18 Page - Microchip Technology |
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18 / 87 page  VSC8540RT DS60001603E-page 18 2022 Microchip Technology Inc. and its subsidiaries FIGURE 5-5: MODE 2 5.2.4 MAC INTERFACE EDGE RATE CONTROL The VSC8540RT device includes programmable control of the rise/fall times for the MAC interface signals. The default setting will select the fastest rise/fall times. However, the fast edge rate will result in higher power consumption on the MAC interface and may result in higher EMI. It is recommended that the user select the appropriate edge rate setting based on the VDDMAC supply voltage, as shown in the following table. In order to further reduce power consumption and EMI, the user may elect to choose a slower edge rate than recom- mended if the end application supports it. The MAC interface signal rise/fall times can be changed by writing to register bits 27E2.7:5. The typical change in edge rate for each setting at various VDDMAC voltages is shown in the following table. These values are based on measurements performed on typical silicon at nominal supply and room temperature set- tings. 5.3 Hardware Mode Strapping and PHY Addressing The VSC8540RT device provides hardware-configured modes of operation that are achieved by sampling output pins on the rising edge of reset and pulling the pin to a logic HIGH or LOW level. If the default logic level set by the internal pulling resistors (detailed in Type column of section Pins by Function) is not the desired one, external stronger 4k7 pull- TABLE 5-4: RECOMMENDED EDGE RATE SETTINGS VDDMAC Voltage Edge Rate Setting 3.3V 100 2.5V 100 1.8V 111 1.5V 111 TABLE 5-5: MAC INTERFACE EDGE RATE CONTROL Register Setting Edge Rate Change (VDDMAC) 3.3V 2.5V 1.8V 1.5V 111 (fastest) Default Default Default (recommended) Default (recommended) 110 –2% –3% –5% –6% 101 –4% –6% –9% –14% 100 –7% (recommended) –10% (recommended) –16% –21% 011 –10% –14% –23% –29% 010 –17% –23% –35% –42% 001 –29% –37% –52% –58% 000 (slowest) –53% –63% –76% –77% MAC SimpliPHY TX_EN TXD[1:0] RX_ER CRS_DV RXD[1:0] TX_EN TXD[1:0] RX_ER CRS_DV RXD[1:0] RMII_CLK TX_EN TXD[1:0] RX_ER RX_CTL RXD[1:0] RMII_CLKIN XTAL1 XTAL2 PLL RMII_CLKOUT 25/50/125 MHz Ref clock TX_ER TX_ER TX_ER |
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