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VSC8540RT 数据表(PDF) 75 Page - Microchip Technology

部件名 VSC8540RT
功能描述  Radiation-Tolerant Single Port Fast Ethernet Copper PHY with RGMII/MII/RMII Interfaces
PDF  87 Pages
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制造商  MICROCHIP [Microchip Technology]
网页  http://www.microchip.com
标志 MICROCHIP - Microchip Technology

VSC8540RT 数据表(HTML) 75 Page - Microchip Technology

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2022 Microchip Technology Inc. and its subsidiaries
DS60001603E-page 75
VSC8540RT
FIGURE 8-7:
COMPENSATED INPUT RGMII TIMING
FIGURE 8-8:
COMPENSATED OUTPUT RGMII TIMING
8.4.11
START OF FRAME INDICATION
This section contains the AC specifications for the SOF indication signals.
TABLE 8-27:
PHY OUTPUT (RX_CLK DELAY WHEN REGISTER 20E2.[6:4]=100’B)
Parameter
Symbol
Minimum
Typical
Maximum Unit
Data to clock setup (RX_CLK
delay = 100’b)
tSETUP_R 1.4
2.0
ns
Clock to data hold (RX_CLK
delay = 100’b)
tHOLD_R 1.5
2.0
ns
TABLE 8-28:
START OF FRAME INDICATION AC CHARACTERISTICS
Parameter
Symbol
Minimum
Typical
Maximum
Unit
Condition
TX_SOF_CLK/
RX_SOF_CLK frequency
fFREQ
125 - 100 ppm 125
125 + 100 ppm MHz
TX_SOF_CLK/
RX_SOF_CLK stability
fSTABILITY
1.75
ppm
TX_SOF_CLK/
RX_SOF_CLK duty cycle
DC
40
60
%
TX_SOF_CLK/
RX_SOF_CLK peak-to-peak jitter
JPPCLK_SOF
350
ps
10 k samples
TX_SOF_CLK/
RX_SOF_CLK rise time
tR
0.9
ns
20% to 80%
TX_SOF_CLK/
RX_SOF_CLK fall time
tF
0.9
ns
20% to 80%
Data to clock output skew (at
PHY) RX_SOF_CLK to RX_SOF
tSKEW_RX_-
SOF
700
1100
ps
tSETUP_T
TXD[3:0]
TX_CTL
TX_CLK
TXD[3:0]
TXD[7:4]
TXEN
TXERR
tHOLD_T
RXD[3:0]
RX_CTL
RX_CLK
RXD[3:0]
RXD[7:4]
RXEN
RXERR
tSETUP_R
RX_CLK with
Internal
Delay Added
tHOLD_R
RX_CLK delay = 100'b



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