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VSC8540RT 数据表(PDF) 41 Page - Microchip Technology

部件名 VSC8540RT
功能描述  Radiation-Tolerant Single Port Fast Ethernet Copper PHY with RGMII/MII/RMII Interfaces
PDF  87 Pages
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制造商  MICROCHIP [Microchip Technology]
网页  http://www.microchip.com
标志 MICROCHIP - Microchip Technology

VSC8540RT 数据表(HTML) 41 Page - Microchip Technology

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2022 Microchip Technology Inc. and its subsidiaries
DS60001603E-page 41
VSC8540RT
6.2.8
AUTO-NEGOTIATION LINK PARTNER NEXT PAGE RECEIVE
The bits in register 8 of the main register space work together with register 7 to determine certain aspects of the LP auto-
negotiation. The following table shows the possible readouts.
6.2.9
MMD ACCESS CONTROL REGISTER
The bits in register 13 of the main register space are a window to the EEE registers as defined in IEEE 802.3az-2010
Clause 45.
6.2.10
MMD ADDRESS OR DATA REGISTER
The bits in register 14 of the main register space are a window to the EEE registers as defined in IEEE 802.3az-2010
Clause 45.
6.2.11
100BASE-TX STATUS EXTENSION
Register 16 in the main registers page space provides additional information about the status of the 100BASE-TX oper-
ation.
TABLE 6-11:
AUTO-NEGOTIATION LP NEXT PAGE RECEIVE, ADDRESS 8 (0X08)
Bit
Name
Access
Description
Default
15
LP next page
RO
1: More pages follow.
0
14
Acknowledge
RO
1: LP acknowledge.
0
13
LP message page
RO
1: Message page.
0: Unformatted page.
0
12
LP acknowledge 2
RO
1: LP complies with request.
0
11
LP toggle
RO
1: Previous transmitted LCW = 0.
0: Previous transmitted LCW = 1.
0
10:0 LP message/unformatted code RO
All zeros
TABLE 6-12:
MMD EEE ACCESS, ADDRESS 13 (0X0D)
Bit
Name
Access
Description
15:14 Function
R/W
00: Address.
01: Data, no post increment.
10: Data, post increment for read and write.
11: Data, post increment for write only.
13:5
Reserved RO
Reserved.
4:0
DVAD
R/W
Device address as defined in IEEE 802.3az-2010 table 45–1.
TABLE 6-13:
MMD ADDRESS OR DATA REGISTER, ADDRESS 14 (0X0E)
Bit
Name
Access
Description
15:0 Register Address/Data R/W
When register 13.15:14 = 2'b00, address of register of the device
that is specified by 13.4:0. Otherwise, the data to be written to or
read from the register.
TABLE 6-14:
100BASE-TX STATUS EXTENSION, ADDRESS 16 (0X10)
Bit
Name
Access
Description
Default
15
100BASE-TX Descrambler
RO
1: Descrambler locked.
0
14
100BASE-TX lock error
RO
Self-clearing bit.
1: Lock error detected.
0
13
100BASE-TX disconnect state
RO
Self-clearing bit.
1: PHY 100BASE-TX link disconnect detected.
0
12
100BASE-TX current link status RO
1: PHY 100BASE-TX link active.
0



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