VSC8540RT datasheet(23/87 Pages) MICROCHIP

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DS60001603E-page 23

VSC8540RT

In addition, the IEEE 802.3az-2010 standard defines a 10BASE-Te mode that reduces transmit signal amplitude from

5V peak-to-peak to approximately 3.3V peak-to-peak. This mode reduces power consumption in 10 Mbps link speed

and fully interoperates with legacy 10BASE-T-compliant PHYs over 100 m Cat5 cable or better.

To configure the VSC8540RT device in 10BASE-Te mode, sets register 17E2.15 to 1 for each port. Additional energy-

efficient Ethernet features are controlled through Clause 45 registers. For more information, see Section 6.6, "Clause

45 Registers to Support Energy-Efficient Ethernet and 802.3bf"

5.5

Reference Clock

The VSC8540RT device supports multiple reference clock input options to allow maximum system level flexibility. There

are two REFCLK_SEL signals available to allow an end user to select between the various options. The following table

shows the functionality and associated reference clock frequency.

The following figure shows a reference tank circuit for a fundamental mode crystal.

Note:

For best performance, traces on PCB should be of similar length and Kelvin-connected to ground.

FIGURE 5-8:

XTAL REFERENCE CLOCK

Note:

Routing capacitance less than 1 pF from each XTAL pin to crystal device.

The following figure shows an external 3.3V reference clock.

TABLE 5-12:

REFCLK FREQUENCY SELECTION

REFCLK_SEL [1:0]

Reference Clock Mode

25 MHz, on-chip oscillator ON (XTAL1/2 pins)

25 MHz, on-chip oscillator OFF (XTAL1 pin)

50 MHz, on-chip oscillator OFF (XTAL1 pin)

125 MHz, on-chip oscillator OFF (XTAL1 pin)

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