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VSC8540RT 数据表(PDF) 29 Page - Microchip Technology |
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VSC8540RT 数据表(HTML) 29 Page - Microchip Technology |
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29 / 87 page ![]() 2022 Microchip Technology Inc. and its subsidiaries DS60001603E-page 29 VSC8540RT When a PHY generates an interrupt, the MDINT pin is asserted by driving low if the interrupt pin enable bit (register 25.15) is set. The MDINT pin is configured for open-drain (active-low) operation. Tie the pin to a pull-up resistor to VDDMDIO. The following illustration shows the configuration. FIGURE 5-14: MDINT CONFIGURED AS AN OPEN-DRAIN (ACTIVE-LOW) PIN 5.11 LED Interface The LED interface supports direct drive and basic serial LED mode configuration. The polarity of the LED outputs is programmable and can be changed using register 17E2, bits 13:10. The default polarity is active low. Direct drive mode provides two LED signals, LED0 and LED1. The mode and function of each LED signal can be con- figured independently. In basic serial LED mode, all signals that can be displayed on LEDs are sent as LED_Data and LED_CLK for external processing. The following table shows the bit 9 settings for register 14G that are used to control the LED behavior for all the LEDs in the VSC8540RT device. 5.11.1 LED MODES Each LED pin can be configured to display different status information that can be selected by setting the LED mode in register 29. The default LED state is active low and can be changed by modifying the value in register 17E2, bits 13:10. The blink/pulse stretch is dependent on the LED behavior setting in register 30. The following table provides a summary of the LED modes and functions. The modes listed are equivalent to the setting used in register 29 to configure each LED pin. TABLE 5-13: LED DRIVE STATE Setting Active Not Active 14G.9 = 1 (default) Ground Tristate 14G.9 = 0 (alternate setting) Ground VDD TABLE 5-14: LED MODE AND FUNCTION SUMMARY Mode Function Name LED State and Description 0 Link/Activity 1: No link in any speed on any media interface. 0: Valid link at any speed on any media interface. Blink or pulse-stretch = Valid link at any speed on any media interface with activity present. 1 Reserved Reserved. 2 Link100/Activity 1: No link in 100BASE-TX. 0: Valid 100BASE-TX. Blink or pulse-stretch = Valid 100BASE-TX link with activity present. 3 Link10/Activity 1: No link in 10BASE-T. 0: Valid 10BASE-T link. Blink or pulse-stretch = Valid 10BASE-T link with activity present. 4 Reserved Reserved. MDINT (to the Station Manager) Interrupt Pin Enable (Register 25.15) Interrupt Pin Status (Register 26.15) External Pull-Up Resistor at the Station Manager VDDMDIO PHY_n MDINT |
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