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VSC8540RT 数据表(PDF) 70 Page - Microchip Technology |
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VSC8540RT 数据表(HTML) 70 Page - Microchip Technology |
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70 / 87 page  VSC8540RT DS60001603E-page 70 2022 Microchip Technology Inc. and its subsidiaries 8.4.2 RECOVERED CLOCK This section provides the AC characteristics for the recovered clock output signal. The following table shows the AC specifications for the RCVRD_CLK output. The following illustration shows the test circuit for the CLKOUT, RCVRD_CLK, and RMII_CLKOUT outputs. FIGURE 8-2: TEST CIRCUIT FOR RECOVERED CLOCK OUTPUTS SIGNAL 8.4.3 CLKOUT This section provides the AC characteristics for the CLKOUT signal. The following table shows the AC specifications for the CLKOUT output. TABLE 8-18: RECOVERED CLOCK AC CHARACTERISTICS Parameter Symbol Minimum Typical Maximum Unit Condition Recovered clock frequency ƒ 125 MHz Recovered clock frequency ƒ 31.25 MHz Recovered clock frequency ƒ 25 MHz Recovered clock cycle time tRCYC 8ns Recovered clock cycle time tRCYC 32 ns Recovered clock cycle time tRCYC 40 ns Frequency stability ƒSTABILITY 50 ppm Duty cycle DC 40 50 60 % Clock rise time and fall time tR, tF 1.2 ns 20% to 80% Peak-to-peak jitter, copper media interface JPPCLK_Cu 400 ps 10k samples. TABLE 8-19: CLKOUT AC CHARACTERISTICS Parameter Symbol Minimum Typical Maximum Unit Condition CLKOUT frequency ƒ 125 MHz CLKOUT frequency ƒ 50 MHz CLKOUT frequency ƒ 25 MHz CLKOUT cycle time tCOCYC 8ns CLKOUT cycle time tCOCYC 20 ns CLKOUT cycle time tCOCYC 40 ns Frequency stability ƒSTABILITY 5 ppm Relative to device REFCLK frequency Duty cycle DC 40 50 60 % CLKOUT at 25 MHz and 125 MHz Duty cycle DC 35 50 75 % CLKOUT at 50 MHz Clock rise time and fall time tR, tF 1.5 ns 20% to 80% Peak-to-peak jitter JPPCLK- OUT 700 ps 10 k samples Device Under Test Signal Measurement Point 50 Ω 1 ns T-line 39 Ω 5.1 pF |
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