VSC8540RT datasheet(27/87 Pages) MICROCHIP

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DS60001603E-page 27

VSC8540RT

In the absence of signal energy on the media pins, the PHY periodically transitions from low-power state to link partner

wake-up state, based on the programmable sleep timer (register bits 20E1.14:13). The actual sleep time duration is ran-

domized from –80 ms to 60 ms to avoid two linked PHYs in ActiPHY mode entering a lock-up state during operation.

5.8.2

LINK PARTNER WAKE-UP STATE

In the link partner wake-up state, the PHY attempts to wake up the link partner. Up to three complete fast link pulse

bursts are sent on alternating pairs A and B of the Cat5 media for a duration based on the wake-up timer, which is set

using register bits 20E1.12:11.

In this state, SMI interface (MDC, MDIO, and MDINT) functionality is provided.

After sending signal energy on the relevant media, the PHY returns to the low power state.

5.8.3

NORMAL OPERATING STATE

In the normal operating state, the PHY establishes a link with a link partner. When the media is unplugged or the link

partner is powered down, the PHY waits for the duration of the programmable link status time-out timer, which is set

using register bit 28.7 and bit 28.2. It then enters the low power state.

5.9

Media Recovered Clock Output

For Synchronous Ethernet applications, VSC8540RT include a recovered clock output pin, RCVRD_CLK, controlled by

To enable recovered clock output, set register 23G bit 15 and bit 0 to 1. By default, the recovered clock output pin is

disabled and held low, including when NRESET is asserted. Register 23G also controls the clock source, the clock fre-

quency (either 25 MHz, 31.25 MHz, or 125 MHz), and squelch conditions.

Note:

When EEE is enabled on a link, the use of the recovered clock output is not recommended due to long hold-

overs occurring during EEE quiet/refresh cycles.

5.9.1

CLOCK OUTPUT SQUELCH

Under certain conditions, such as when there is no link present or during auto-negotiation, the PHY outputs a clock

based on the REFCLK pin. To prevent an undesirable clock from appearing on the recovered clock pins, the

VSC8540RT device squelches, or inhibits, the clock output based on any of the following criteria:

• No link is detected (the link status register 1, bit 2 = 0).

• The link is found to be unstable using the fast link failure detection feature. The FASTLINK-FAIL pin is asserted

high when enabled.

• The active link is in 10BASE-T.This mode produces unreliable recovered clock sources.

• CLK_SQUELCH_IN is enabled to squelch the clock.

Use register 23G bits 5:4 to configure the clock squelch criteria. This register can also disable the squelch feature. The

CLK_SQUELCH_IN pin controls the squelching of the clock. The recovered clock output is squelched when the

CLK_SQUELCH_IN pin is high. CLK_SQUELCH_IN pin has an internal PD and can be left unconnected.

5.10

Serial Management Interface

The VSC8540RT device includes an IEEE 802.3-compliant Serial Management Interface (SMI) that is affected by use

of its MDC and MDIO pins. The SMI provides access to device control and status registers. The register set that controls

the SMI consists of 32 16-bit registers, including all required IEEE-specified registers. Additional pages of registers are

accessible using device register 31.

Energy-efficient Ethernet control registers are available through the SMI using Clause 45 registers and Clause 22 reg-

ister access in registers 13 through 14.

The SMI is a synchronous serial interface with input data to the VSC8540RT device on the MDIO pin that is clocked on

the rising edge of the MDC pin. The output data is sent on the MDIO pin on the rising edge of the MDC signal. The

interface can be clocked at a rate from 0 MHz to 12.5 MHz, depending on the total load on MDIO. An external 2 k



pull-up resistor is required on the MDIO pin.

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