VSC8540RT datasheet(19/87 Pages) MICROCHIP

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DS60001603E-page 19

VSC8540RT

ing resistors need to be added to your design. These output pins are required by the device as inputs while NRESET is

asserted and the logic state of the pin is latched in the device upon de-assertion of NRESET. To ensure correct operation

of the hardware strapping function, any other device connected to these pins must not actively drive a signal onto them.

The following table describes the pins used for this purpose and their respective modes.

5.3.1

CLKOUT SIGNAL CONFIGURATION

When the CLKOUT signal is pulled LOW and the state of that signal is latched to logic 0 on the rising edge of reset, the

CLKOUT output is disabled and the device will drive a logic low level on that pin after reset de-assertion. When the CLK-

OUT signal is pulled HIGH and the state of that signal is latched to logic 1, the CLKOUT output is enabled. This behavior

can also be controlled through register 13G.15.

The CLKOUT signal is frequency-locked to the reference clock signal input through XTAL1/XTAL2 pins. The frequency

of CLKOUT can be programed to the following values through register 13G.14:13:

•25 MHz

•50 MHz

• 125 MHz

5.3.2

MANAGED MODE

When RX_CLK pin is pulled LOW and the state of that signal is latched to logic 0 on the rising edge of reset, the device

operates in a managed mode. In managed mode, the remaining 5 signals (A–E) are used to set the PHY address, allow-

ing up to 32 devices to reside on the shared MDIO bus. In this mode, the device can be configured using register access

and no additional hardware configurability is provided. The following table lists the assigned PHY address values in

managed mode.

5.3.3

UNMANAGED MODE

When RX_CLK is pulled HIGH and the state of that signal is latched to logic 1 on the rising edge of reset, the device

operates in an unmanaged mode. The signals A–E are used to set default chip configurations, as described in the fol-

lowing sections.

Note:

The default values for the following registers depend on the chosen hardware strapping options.

• 0.13, 0.6—Forced speed selection

TABLE 5-6:

HARDWARE MODE STRAPPING AND PHY ADDRESSING

Pin(s)

Operation Mode

CLKOUT

Enable/disable CLKOUT signal

RX_CLK

Managed or unmanaged mode

RXD0

Signal A

RXD1

Signal B

RXD2

Signal C

RXD3

Signal D

RX_DV/RX_CTL

Signal E

MII_TXCLK

Select MII or RGMII/RMII MAC interface mode

RXD4

PHY address bit 0 in unmanaged mode

RXD5

PHY address bit 1 in unmanaged mode

RXD6

CLKOUT frequency selection bit 0

RXD7

CLKOUT frequency selection bit 1

TABLE 5-7:

MANAGED MODE

Signal

PHY Address Values

Signal A

PHY address bit 0

Signal B

PHY address bit 1

Signal C

PHY address bit 2

Signal D

PHY address bit 3

Signal E

PHY address bit 4

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