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VSC8540RT 数据表(PDF) 52 Page - Microchip Technology |
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VSC8540RT 数据表(HTML) 52 Page - Microchip Technology |
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52 / 87 page ![]() VSC8540RT DS60001603E-page 52 2022 Microchip Technology Inc. and its subsidiaries 6.4 Extended Page 2 Registers To access the extended page 2 registers (16E2–30E2), enable extended register access by writing 0x0002 to register 31. For more information, see Table 6-27. When extended page 2 register access is enabled, reads and writes to registers 16–30 affect the extended registers 16E2–30E2 instead of those same registers in the IEEE-specified register space. Registers 0–15 are not affected by the state of the extended page register access. Writing 0x0000 to register 31 restores the main register access. The following table lists the addresses and register names in the extended register page 2 space. These registers are accessible only when the device register 31 is set to 0x0002. 6.4.1 CU PMD TRANSMIT CONTROL The register at address 16E2 consists of the bits that provide control over the amplitude settings for the transmit side Cu PMD interface. These bits provide the ability to make small adjustments in the signal amplitude to compensate for minor variations in the magnetics from different vendors. Extreme caution must be exercised when changing these set- tings from the default values as they have a direct impact on the signal quality. Changing these settings also affects the linearity and harmonic distortion of the transmitted signals. For help with changing these values, contact your Microchip representative . TABLE 6-35: EXTENDED REGISTERS PAGE 2 SPACE Address Name 16E2 Cu PMD Transmit Control 17E2 EEE Control 18E2–19E2 Reserved 20E2 RGMII Control 21E2 Wake-on-LAN MAC Address [15:0] 22E2 Wake-on-LAN MAC Address [31:16] 23E2 Wake-on-LAN MAC Address [47:32] 24E2 Secure-On Password [15:0] 25E2 Secure-On Password [31:16] 26E2 Secure-On Password [47:32] 27E2 Wake-on-LAN and MAC Interface Control 28E2 Extended Interrupt Mask 29E2 Extended Interrupt Status 30E2 Reserved TABLE 6-36: CU PMD TRANSMIT CONTROL, ADDRESS 16E2 (0X10) Bit Name Access Description Default 15:12 Reserved RO Reserved |
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