VSC8540RT datasheet(17/87 Pages) MICROCHIP

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DS60001603E-page 17

VSC8540RT

Even though the RMII specification does not call for the use of TX_ER signal, it is required in order to support Energy-

Efficient Ethernet (802.3az).

5.2.3.2

RMII Clocking Overview

When the device is in RMII mode, the clock inputs to the device need to support the various modes in which RMII device

can operate. There are two basic modes of operation in RMII mode:

• Mode 1—system provides a 50 MHz clock that is used to clock the RMII interface and must be used as the chip

reference clock.

• Mode 2—PHY operates from a 25 MHz or 125 MHz reference clock, and sources the 50 MHz clock used for the

RMII interface.

These two modes of operation and the clocking schemes are described in the following sections.

5.2.3.2.1

Mode 1

In this mode of operation, an external source is used to provide a 50 MHz clock through the RMII_CLKIN and the XTAL1

pin. This 50 MHz clock is used as the main clock for the RMII interface, and must be used as the reference clock for the

PHY connected to the XTAL1 pin. There is no phase requirement concerning the clock arrival at the RMII_CLKIN pin

as compared to the XTAL1 pin. In this mode, the RMII_CLKOUT signal from the PHY is not used. The RMII_CLKOUT

is enabled by default and that clock output should be disabled through register 27E2.4. The following figure illustrates

RMII signal connections at the system level.

FIGURE 5-4:

MODE 1

5.2.3.2.2

Mode 2

In this mode of operation, the PHY operates from a 25 MHz crystal (XTAL1 and XTAL2) or 25 MHz/50 MHz/125 MHz

single-ended external clock (XTAL1), and sources the 50 MHz clock required for the RMII interface. This 50 MHz clock

is output from the PHY on the RMII_CLKOUT pin and then connected to the MAC and PHY RMII_CLKIN signals. In this

mode, the PHY generates a 50 MHz clock for the system and that clock output is enabled. The following figure illustrates

RMII signal connections at the system level.

TXD3

TX_ER (to support 802.3az)

TXD1

TXD0

TX_EN/TX_CTL

TX_EN

RXD1

RXD0

RXD3

RX_ER

RX_DV/RX_CTL

CRS_DV

TABLE 5-3:

RMII PIN ALLOCATION (CONTINUED)

Chip Pin

RMII Signal

MAC

SimpliPHY

TX_EN

TXD[1:0]

RX_ER

CRS_DV

RXD[1:0]

50 MHz clock

TX_EN

TXD[1:0]

RX_ER

CRS_DV

RXD[1:0]

RMII_CLK

TX_EN

TXD[1:0]

RX_ER

RX_CTL

RXD[1:0]

RMII_CLKIN

XTAL2

PLL

RMII_CLKOUT

XTAL1

TX_ER

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