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VSC8540RT 数据表(PDF) 46 Page - Microchip Technology |
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VSC8540RT 数据表(HTML) 46 Page - Microchip Technology |
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46 / 87 page  VSC8540RT DS60001603E-page 46 2022 Microchip Technology Inc. and its subsidiaries 6.2.20 INTERRUPT STATUS The status of interrupts already written to the device is available for reading from register 26 in the main registers space. The following table shows the expected readouts. The following information applies to the interrupt status bits: • All set bits in this register are cleared after being read (self-clearing). If bit 26.15 is set, the cause of the interrupt can be read by reading bits 26.14:0. • For bits 26.14 and 26.12, bit 0.12 must be set for this interrupt to assert. • For bit 26.0, this interrupt will not occur when RX_ER is used for carrier-extension decoding of a link partner's data transmission. • If bit 5 is set, register 29E2 must be read to determine the source of the interrupt. 6.2.21 DEVICE AUXILIARY CONTROL AND STATUS Register 28 provides control and status information for several device functions not controlled or monitored by other device registers. The following table shows the settings available and the expected readouts. TABLE 6-23: INTERRUPT STATUS, ADDRESS 26 (0X1A) Bit Name Access Description Default 15 Interrupt status RO Self-clearing bit. 1: Interrupt pending. 0 14 Speed state change status RO Self-clearing bit. 1: Interrupt pending. 0 13 Link state change status RO Self-clearing bit. 1: Interrupt pending. 0 12 FDX state change status RO Self-clearing bit. 1: Interrupt pending. 0 11 Autonegotiation error status RO Self-clearing bit. 1: Interrupt pending. 0 10 Autonegotiation complete status RO Self-clearing bit. 1: Interrupt pending. 0 9 Inline powered device detect status RO Self-clearing bit. 1: Interrupt pending. 0 8 Symbol error status RO Self-clearing bit. 1: Interrupt pending. 0 7 Fast link failure detect status RO Self-clearing bit. 1: Interrupt pending. 0 6 Wake-on-LAN event status RO Self-clearing bit. 1: Interrupt pending. 0 5 Extended interrupt status RO Self-clearing bit. 1: Interrupt pending. 0 4 Reserved RO Reserved. 3 False carrier interrupt status RO Self-clearing bit. 1: Interrupt pending. 0 2 Reserved RO Reserved. 1 Reserved RO Reserved. 0 RX_ER interrupt status RO Self-clearing bit. 1: Interrupt pending. 0 TABLE 6-24: AUXILIARY CONTROL AND STATUS, ADDRESS 28 (0X1C) Bit Name Access Description Default 15 Autonegotiation complete RO Duplicate of bit 1.5 when auto-negotiation is enabled, otherwise this is the current link sta- tus. 0 14 Autonegotiation disabled RO Inverted duplicate of bit 0.12. 0 13 HP Auto-MDIX crossover indication RO 1: HP Auto-MDIX crossover performed inter- nally. 0 12 Reserved RO Reserved. 11 A polarity inversion RO 1: Polarity swap on pair A. 0 10 B polarity inversion RO 1: Polarity swap on pair B. 0 9:8 Reserved RO Reserved. |
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