VSC8540RT datasheet(26/87 Pages) MICROCHIP

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VSC8540RT

DS60001603E-page 26

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5.8

ActiPHY Power Management

In addition to the IEEE-specified power down control bit (device register bit 0.11), the VSC8540RT device also includes

ActiPHY power management mode for each PHY. This mode enables support for power-sensitive applications. It utilizes

a signal-detect function that monitors the media interface for the presence of a link to determine when to automatically

power down the PHY. The PHY wakes up at a programmable interval and attempts to wake up the link partner PHY by

sending a burst of fast link pulse over copper media.

The ActiPHY power management mode is enabled on a per-port basis during normal operation at any time by setting

The following operating states are possible when ActiPHY mode is enabled:

• Low power state

• Link partner wake-up state

• Normal operating state (link-up state)

The VSC8540RT device switches between the low power state and link partner wake-up state at a programmable rate

(the default is two seconds) until signal energy has been detected on the media interface pins. When signal energy is

detected, the PHY enters the normal operating state. If the PHY is in its normal operating state and the link fails, the

PHY returns to the low power state after the expiration of the link status time-out timer. After reset, the PHY enters the

low power state.

When auto-negotiation is enabled in the PHY, the ActiPHY state machine operates as described.

When auto-negotiation is disabled and the link is forced to use 10BASE-T or 100BASE-TX modes while the PHY is in

its low power state, the PHY continues to transition between the low power and link partner wake-up states until signal

energy is detected on the media pins. At that time, the PHY transitions to the normal operating state and stays in that

state even when the link is dropped. When auto-negotiation is disabled while the PHY is in the normal operation state,

the PHY stays in that state when the link is dropped and does not transition back to the low power state.

The following illustration shows the relationship between ActiPHY states and timers.

FIGURE 5-11:

ACTIPHY STATE DIAGRAM

5.8.1

LOW POWER STATE

In the low power state, all major digital blocks are powered down. However, the SMI interface (MDC, MDIO, and MDINT)

functionality is provided.

In this state, the PHY monitors the media interface pins for signal energy. The PHY comes out of low power state and

transitions to the normal operating state when signal energy is detected on the media. This happens when the PHY is

connected to an auto-negotiation-capable link partner or another PHY in enhanced ActiPHY link partner wake-up state.

Low Power State

LP Wake-up

State

Normal

Operation State

Signal Energy Detected on

Media

Timeout Timer Expires and

Auto-negotiation Enabled

Sleep Timer Expires

FLP Burst or

Clause 37 Restart

Signal Sent

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