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VSC8540RT 数据表(PDF) 42 Page - Microchip Technology

部件名 VSC8540RT
功能描述  Radiation-Tolerant Single Port Fast Ethernet Copper PHY with RGMII/MII/RMII Interfaces
PDF  87 Pages
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制造商  MICROCHIP [Microchip Technology]
网页  http://www.microchip.com
标志 MICROCHIP - Microchip Technology

VSC8540RT 数据表(HTML) 42 Page - Microchip Technology

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VSC8540RT
DS60001603E-page 42
2022 Microchip Technology Inc. and its subsidiaries
6.2.12
BYPASS CONTROL
The bits in this register control aspects of functionality in effect when the device is disabled for the purpose of traffic
bypass. The following table shows the settings available.
6.2.13
ERROR COUNTER 1
The bits in register 19 provide an error counter. The following table shows the settings available.
11
100BASE-TX receive error
RO
Self-clearing bit.
1: Receive error detected.
0
10
100BASE-TX transmit error
RO
Self-clearing bit.
1: Transmit error detected.
0
9
100BASE-TX SSD error
RO
Self-clearing bit.
1: Start-of-stream delimiter error detected.
0
8
100BASE-TX ESD error
RO
Self-clearing bit.
1: End-of-stream delimiter error detected.
0
7:0 Reserved
RO
Reserved.
TABLE 6-15:
BYPASS CONTROL, ADDRESS 18 (0X12)
Bit
Name
Access
Description
Default
15
Transmit disable
R/W
1: PHY transmitter disabled.
0
14
4B5B encoder/decoder
R/W
1: Bypass 4B/5B encoder/decoder.
0
13
Scrambler
R/W
1: Bypass scrambler.
0
12
Descrambler
R/W
1: Bypass descrambler.
0
11
PCS receive
R/W
1: Bypass PCS receiver.
0
10
PCS transmit
R/W
1: Bypass PCS transmit.
0
9
LFI timer
R/W
1: Bypass Link Fail Inhibit (LFI) timer.
0
8
Reserved
RO
Reserved.
7
HP Auto-MDIX at forced 10/
100
R/W
Sticky bit.
1: Disable HP Auto-MDIX at forced 10/100 speeds.
1
6
Reserved
R/W
Reserved.
0
5
Disable pair swap correction
(HP Auto-MDIX when auto-
negotiation enabled)
R/W
Sticky bit.
1: Disable the automatic pair swap correction.
0
4
Disable polarity correction
R/W
Sticky bit.
1: Disable polarity inversion correction on each subchannel.
0
3
Parallel detect control
R/W
Sticky bit.
1: Do not ignore advertised ability.
0: Ignore advertised ability.
1
2:0 Reserved
RO
Reserved.
TABLE 6-16:
EXTENDED CONTROL AND STATUS, ADDRESS 19 (0X13)
Bit
Name
Access
Description
Default
15:8 Reserved
RO
Reserved.
7:0
Receive error counter
RO
8-bit counter that saturates when it reaches 255.
These bits are self-clearing when read.
0x00
TABLE 6-14:
100BASE-TX STATUS EXTENSION, ADDRESS 16 (0X10) (CONTINUED)
Bit
Name
Access
Description
Default



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