VSC8540RT datasheet(43/87 Pages) MICROCHIP

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DS60001603E-page 43

VSC8540RT

6.2.14

ERROR COUNTER 2

The bits in register 20 provide an error counter. The following table shows the settings available.

6.2.15

ERROR COUNTER 3

The bits in register 21 provide an error counter. The following table shows the settings available.

6.2.16

EXTENDED CONTROL AND STATUS

The bits in register 22 provide additional device control and readouts. The following table shows the settings available.

The following information applies to the extended control and status bits:

• When bit 22.15 is set, the link integrity state machine is bypassed and the PHY is forced into a link pass status.

• When bits 22.11:10 are set to 00, the squelch threshold levels are based on the IEEE standard for 10BASE-T.

When set to 01, the squelch level is decreased, which can improve the bit error rate performance on long loops.

TABLE 6-17:

EXTENDED CONTROL AND STATUS, ADDRESS 20 (0X14)

Bit

Name

Access

Description

Default

15:8 Reserved

Reserved.

7:0

False carrier counter

8-bit counter that saturates when it reaches 255.

These bits are self-clearing when read.

0x00

TABLE 6-18:

EXTENDED CONTROL AND STATUS, ADDRESS 21 (0X15)

Bit

Name

Access

Description

Default

15:8 Reserved

Reserved.

7:0

Copper media link disconnect counter RO

8-bit counter that saturates when it reaches

255. These bits are self-clearing when read.

0x00

TABLE 6-19:

EXTENDED CONTROL AND STATUS, ADDRESS 22 (0X16)

Bit

Name

Access

Description

Default

Force 10BASE-T link high

R/W

Sticky bit.

1: Bypass link integrity test.

0: Enable link integrity test.

Jabber detect disable

R/W

Sticky bit.

1: Disable jabber detect.

Disable 10BASE-T echo

R/W

Sticky bit.

1: Disable 10BASE-T echo.

Disable SQE mode

R/W

Sticky bit.

1: Disable SQE mode.

11:10

10BASE-T squelch control

R/W

Sticky bit.

00: Normal squelch.

01: Low squelch.

10: High squelch.

11: Reserved.

Sticky reset enable

R/W

Super-sticky bit.

1: Enabled.

EOF Error

This bit is self-clearing.

1: EOF error detected.

10BASE-T disconnect state RO

This bit is self-clearing.

1: 10BASE-T link disconnect detected.

10BASE-T link status

1: 10BASE-T link active.

5:1

Reserved

Reserved.

SMI broadcast write

R/W

Sticky bit.

1: Enabled.

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