VSC8540RT datasheet(33/87 Pages) MICROCHIP

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DS60001603E-page 33

VSC8540RT

5.15

Start of Frame (SOF) Indication

The VSC8540RT device includes support for IEEE 1588 timing by generating a SOF pulse when the Start of Frame

Delimiter (SFD, octet 0xD5) is detected by the PCS engine. The pulse indicates the actual time the SFD symbol is

received at the PCS. There is a fixed timing relationship from the time the SFD arrives at the PCS to when it appears

on the line in the receive or transmit direction. Use of this signal decreases the additional variability in timing from the

MAC interface to the PCS that can result from multiple clock domain crossings. For 100BASE-TX, the SOF signal can

have variability of ±4 ns.

The SOF pulse is generated in both transmit and receive directions and the associated clocks used in the PCS engines

are also output to chip pins to provide an accurate timing reference. These signals are multiplexed onto the higher order

GMII signals and are only available when using the RGMII or RMII interface modes. To enable this functionality, set reg-

ister bit 20E2.12 to 1.

FIGURE 5-16:

SOF INDICATION

5.16

Forced Speed Mode Link-Up Timing

The following table specifies the time the device will take to establish a link when operating in a forced speed mode.

In 100Base-TX mode, HP Auto-MDIX can be disabled by setting register 18 bit 7.

Link-up times are given for previously-configured PHYs on each side of the link— that is, the times do not include con-

figuration time prior to attempting link-up. Both the device and link partner must be configured in forced speed mode to

achieve the listed link-up times.

5.17

Testing Features

The VSC8540RT device includes several testing features designed to facilitate performing system-level debugging and

in-system production testing. This section describes the available features.

5.17.1

ETHERNET PACKET GENERATOR

The Ethernet Packet Generator (EPG) can be used at each of the 10/100BASE-TX speed settings for copper Cat5

media to isolate problems between the MAC and the VSC8540RT device, or between a locally connected PHY and its

remote link partner. Enabling the EPG feature disables all MAC interface transmit pins and selects the EPG as the

source for all data transmitted onto the twisted pair interface.

Note:

The EPG is intended for use with laboratory or in-system testing equipment only. Do not use the EPG testing

feature when the VSC8540RT device is connected to a live network.

To enable the EPG feature, set the device register bit 29E1.15 to 1.

TABLE 5-17:

SOF INDICATION

Signal

RXD7

RX_SOF

RXD6

RX_SOF_CLK

RXD5

TX_SOF

RXD4

TX_SOF_CLK

TABLE 5-18:

FORCED SPEED MODE LINK-UP TIMING

Forced Mode

Minimum Maximum Units

100Base-TX, HP Auto-MDIX Disabled

240

100Base-TX, HP Auto-MDIX Enabled

4000

CLK

DATA

SOF

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