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VSC8540RT 数据表(PDF) 48 Page - Microchip Technology |
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VSC8540RT 数据表(HTML) 48 Page - Microchip Technology |
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48 / 87 page ![]() VSC8540RT DS60001603E-page 48 2022 Microchip Technology Inc. and its subsidiaries Note: Bits 30.11:10 are active only in port 0 and affect the behavior of LEDs for all the ports. 6.2.24 EXTENDED PAGE ACCESS To provide functionality beyond the IEEE 802.3-specified registers and main device registers, an extended set of regis- ters provide an additional 15 register spaces. The register at address 31 controls access to the extended registers. Accessing the GPIO page register space is similar to accessing the extended page registers. The following table shows the settings available. 6.3 Extended Page 1 Registers To access the extended page 1 registers (17E1–30E1), enable extended register access by writing 0x0001 to register 31. Writing 0x0000 to register 31 restores the main register access. When extended page 1 register access is enabled, reads and writes to registers 16–30 affect the extended registers 17E1–30E1 instead of those same registers in the IEEE-specified register space. Registers 0–15 are not affected by the state of the extended page register access. 11:10 LED blink/pulse-stretch rate R/W Sticky bit. 00: 2.5 Hz blink rate/400 ms pulse-stretch. 01: 5 Hz blink rate/200 ms pulse-stretch. 10: 10 Hz blink rate/100 ms pulse-stretch. 11: 20 Hz blink rate/50 ms pulse-stretch. The blink rate selection sets the rate used for all LED pins. 01 9:7 Reserved RO Reserved. 6 LED1 pulse-stretch/blink select R/W Sticky bit. 1: Pulse-stretch. 0: Blink. 0 5 LED0 pulse-stretch/blink select R/W Sticky bit. 1: Pulse-stretch. 0: Blink. 0 4:2 Reserved RO Reserved. 1 LED1 combine feature disable R/W Sticky bit. 0: Combine enabled (link/activity, duplex/collision). 1: Disable combination (link only, duplex only). 0 0 LED0 combine feature disable R/W Sticky bit. 0: Combine enabled (link/activity, duplex/collision). 1: Disable combination (link only, duplex only). 0 TABLE 6-27: EXTENDED/GPIO REGISTER PAGE ACCESS, ADDRESS 31 (0X1F) Bit Name Access Description Default 15:0 Extended/GPIO page register access R/W 0x0000: Register 16–30 accesses main register space. Writ- ing 0x0000 to register 31 restores the main register access. 0x0001: Registers 16–30 access extended register space 1. 0x0002: Registers 16–30 access extended register space 2. 0x0010: Registers 0–30 access GPIO register space. 0x0000 TABLE 6-28: EXTENDED REGISTERS PAGE 1 SPACE Address Name 17E1 Reserved 18E1 Cu Media CRC Good Counter 19E1 Extended Mode Control TABLE 6-26: LED BEHAVIOR, ADDRESS 30 (0X1E) (CONTINUED) Bit Name Access Description Default |
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