VSC8540RT datasheet(20/87 Pages) MICROCHIP

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VSC8540RT

DS60001603E-page 20

 2022 Microchip Technology Inc. and its subsidiaries

• 0.12—Enable autonegotiation

• 0.8—Duplex

• 23.12:11—MAC interface selection

• 19E1.3:2—Force MDI crossover

• 20E2.6:4—RX_CLK delay

• 20E2.2:0—TX_CLK delay

Additionally, the following registers are set to 1 by default in unmanaged mode.

• 28.6—ActiPHY enable

5.3.3.1

Signals A and B

Signals A and B are used to set the RGMII RX_CLK and TX_CLK delay settings (as defined in register 20E2), as per

the following table.

5.3.3.2

Signals C and D

Signals C and D are used to select the link advertisement settings, as defined in the following table.

5.3.3.3

Signal E

Signal E is used to select between RMII and RGMII MAC interface modes. When the state of Signal E is latched to logic

0 on the rising edge of reset, the device operates in RGMII mode. When the state of Signal E is latched to logic 1 on the

rising edge of reset, the device operates in RMII mode.

Note:

RMII only supports 10/100 Mbps speeds. When RMII mode is selected, the link advertisement selection

must also be changed to either 01, 10, or 11 settings, as defined in Table 5-9.

Note:

Correct configuration of the device is an end user responsibility, and no attempt is made in the device to

disallow incorrect configurations.

Additionally, in unmanaged mode, the following settings are changed from their default values:

• Enable ActiPHY (register 28.6 set to 1)

5.3.3.4

PHY Address Bit 0/1 Selection in Unmanaged Mode

The RXD4 and RXD5 pins can be pulled LOW or HIGH to set the bit 0 and bit 1 of the device PHY address. The upper

3 bits of the PHY address are always set to 0, and the lower 2 bits can be set to one of 4 possible combinations through

this external strapping option to provide a total of 4 PHY addresses in unmanaged operation.

5.3.4

MII OR RGMII/RMII MAC INTERFACE MODE

When MII_TXCLK pin is pulled LOW and the state of that signal is latched to logic 0 on the rising edge of reset, the

device operates in a RGMII mode. When MII_TXCLK pin is pulled HIGH and the state of that signal is latched to logic

1 on the rising edge of reset, the device operates in MII mode. This signal is bonded out to a package pin.

Note:

If unmanaged mode is selected and Signal E is latched as a logic 1 (indicating RMII mode), the device will

default to RMII mode regardless of the latched state of the MII_TXCLK.

TABLE 5-8:

SIGNALS A AND B

Signals A, B

RX_CLK and TX_CLK Delay Setting

0, 0

000 - 0.2 ns

0, 1

010 - 1.1 ns

1, 0

100 - 2.0 ns

1, 1

110 - 2.6 ns

TABLE 5-9:

SIGNALS C AND D

Signals C, D

Link Advertisement

0, 0/1

Default mode of operation, 10/100 FDX/HDX, autoneg ON

1, 0

100BTX, HDX forced mode, autoneg OFF

1, 1

10BT, HDX forced mode, autoneg OFF

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