LSM6DST datasheet(45/180 Pages) STMICROELECTRONICS

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LSM6DST

Digital interfaces

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5.3

I²C/I3C coexistence in LSM6DST

In the LSM6DST, the SDA and SCL lines are common to both I²C and I3C. The I²C bus

requires anti-spike filters on the SDA and SCL pins that are not compatible with I3C timing.

The device can be connected to both I²C and I3C or only to the I3C bus depending on the

connection of the INT1 pin when the device is powered up:



INT1 pin floating (internal pull-down): I²C/I3C both active, see Figure 13



INT1 pin connected to VDD_IO: only I3C active, see Figure 14

Figure 13. I²C and I3C both active (INT1 pin not connected)

1. Address assignment (DAA or ENTDA) must be performed with I²C Fast Mode Plus Timing. When the slave

is addressed, the I²C slave is disabled and the timing is compatible with I3C specifications.

Figure 14. Only I3C active (INT1 pin connected to VDD_IO)

1. When the slave is I3C only, the I²C slave is always disabled. The address can be assigned using I3C SDR

timing.

I²C/I3C

(both active)

Master sends

I²C r/w

I²C bus case

Slave performs

requested r/w

Master assigns DA

to the slave(1)

I3C bus case

I3C private R/W with and without 7Eh

CCC commands

Slave event management

Error detection and recovery

Master resets

INT1 pin not connected

I²C/I3C both active

I²C/I3C

I3C bus case

Dynamic

Address

Assignment

Master resets

I3C private R/W with and without 7Eh

CCC commands

Slave event management

Error detection and recovery

(1)

INT1 pin connected to VDD_IO

Only I3C active

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