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LSM6DST 数据表(PDF) 96 Page - STMicroelectronics |
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LSM6DST 数据表(HTML) 96 Page - STMicroelectronics |
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96 / 180 page  Register description LSM6DST 96/180 DocID033525 Rev 2 9.37 STATUS_MASTER_MAINPAGE (39h) Sensor hub source register (r). 9.38 FIFO_STATUS1 (3Ah) FIFO status register 1 (r) Table 112. FIFO_STATUS1 register description Table 109. STATUS_MASTER_MAINPAGE register WR_ ONCE_ DONE SLAVE3_ NACK SLAVE2_ NACK SLAVE1_ NACK SLAVE0_ NACK 00 SENS_HUB_ ENDOP Table 110. STATUS_MASTER_MAINPAGE register description WR_ONCE_DONE When the bit WRITE_ONCE in MASTER_CONFIG (14h) is configured as 1, this bit is set to 1 when the write operation on slave 0 has been performed and completed. Default value: 0 SLAVE3_NACK This bit is set to 1 if Not acknowledge occurs on slave 3 communication. Default value: 0 SLAVE2_NACK This bit is set to 1 if Not acknowledge occurs on slave 2 communication. Default value: 0 SLAVE1_NACK This bit is set to 1 if Not acknowledge occurs on slave 1 communication. Default value: 0 SLAVE0_NACK This bit is set to 1 if Not acknowledge occurs on slave 0 communication. Default value: 0 SENS_HUB_ENDOP Sensor hub communication status. Default value: 0 (0: sensor hub communication not concluded; 1: sensor hub communication concluded) Table 111. FIFO_STATUS1 register DIFF_ FIFO_7 DIFF_ FIFO_6 DIFF_ FIFO_5 DIFF_ FIFO_4 DIFF_ FIFO_3 DIFF_ FIFO_2 DIFF_ FIFO_1 DIFF_ FIFO_0 DIFF_ FIFO_[7:0] Number of unread sensor data (TAG + 6 bytes) stored in FIFO In conjunction with DIFF_FIFO[9:8] in FIFO_STATUS2 (3Bh). |
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