LSM6DST datasheet(37/180 Pages) STMICROELECTRONICS

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LSM6DST

Digital interfaces

180

I²C operation

The transaction on the bus is started through a START (ST) signal. A START condition is

defined as a HIGH to LOW transition on the data line while the SCL line is held HIGH. After

this has been transmitted by the master, the bus is considered busy. The next byte of data

transmitted after the start condition contains the address of the slave in the first 7 bits and

the eighth bit tells whether the master is receiving data from the slave or transmitting data to

the slave. When an address is sent, each device in the system compares the first seven bits

after a start condition with its address. If they match, the device considers itself addressed

by the master.

The Slave ADdress (SAD) associated to the LSM6DST is 110101xb. The SDO/SA0 pin can

be used to modify the less significant bit of the device address. If the SDO/SA0 pin is

connected to the supply voltage, LSb is ‘1’ (address 1101011b); else if the SDO/SA0 pin is

connected to ground, the LSb value is ‘0’ (address 1101010b). This solution permits to

connect and address two different inertial modules to the same I²C bus.

Data transfer with acknowledge is mandatory. The transmitter must release the SDA line

during the acknowledge pulse. The receiver must then pull the data line LOW so that it

remains stable low during the HIGH period of the acknowledge clock pulse. A receiver

which has been addressed is obliged to generate an acknowledge after each byte of data

received.

The I²C embedded inside the LSM6DST behaves like a slave device and the following

protocol must be adhered to. After the start condition (ST) a slave address is sent, once a

slave acknowledge (SAK) has been returned, an 8-bit sub-address (SUB) is transmitted.

The increment of the address is configured by the CTRL3_C (12h) (IF_INC).

The slave address is completed with a Read/Write bit. If the bit is ‘1’ (Read), a repeated

START (SR) condition must be issued after the two sub-address bytes; if the bit is ‘0’ (Write)

the master will transmit to the slave with direction unchanged. Table 11 explains how the

SAD+Read/Write bit pattern is composed, listing all the possible configurations.

Table 11. SAD+Read/Write patterns

Command

SAD[6:1]

SAD[0] = SA0

R/W

SAD+R/W

Read

110101

11010101 (D5h)

Write

110101

11010100 (D4h)

Read

110101

11010111 (D7h)

Write

110101

11010110 (D6h)

Table 12. Transfer when master is writing one byte to slave

Master

SAD + W

SUB

DATA

Slave

SAK

Table 13. Transfer when master is writing multiple bytes to slave

Master

SAD + W

SUB

DATA

Slave

SAK

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