APR2SLASHD datasheet(14/101 Pages) NXP

14 / 101 page

1-8

DSP56001A/D, Rev. 1

MOTOROLA

DSP56001A

Host Interface (HI) Port

HOST INTERFACE (HI) PORT

Table 1-9

HI Signals

Signal

Name

Signal

Type

State

during

Reset

Signal Description

H0–H7

PB0–PB7

Input/

Output

Input or

Output

Tri-stated Host Data Bus (H0–H7)—This data bus transfers data between the

host processor and the DSP56001A. When configured as a Host

Interface port, the H0–H7 signals are tri-stated as long as HEN is

deasserted. The signals are inputs unless HR/W is high and HEN is

asserted, in which case H0–H7 become outputs, allowing the host

processor to read the DSP56001A data. H0–H7 become outputs when

HACK is asserted during HREQ assertion.

Port B GPIO 0–7 (PB0–PB7)

—These signals are GPIO signals (PB0–

PB7) when the Host Interface is not selected.

After reset, the default state for these signals is GPIO input.

HA0–HA2

PB8–PB10

Input

Input or

Output

Tri-stated Host Address 0 – Host Address 2 (HA0–HA2)—These inputs

provide the address selection for each Host Interface register.

Port B GPIO 8–10 (PB8–PB10)

—These signals are GPIO signals (PB8–

PB10) when the Host Interface is not selected.

After reset, the default state for these signals is GPIO input.

HR/W

PB11

Input

Input or

Output

Tri-stated Host Read/Write—This input selects the direction of data transfer for

each host processor access. If HR/W is high and HEN is asserted, H0–

H7 are outputs and DSP data is transferred to the host processor. If

HR/W is low and HEN is asserted, H0–H7 are inputs and host data is

transferred to the DSP. HR/W must be stable when HEN is asserted.

Port B GPIO 11 (PB11)

—This signal is a GPIO signal called PB11

when the Host Interface is not being used.

After reset, the default state for this signal is GPIO input.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

APR2/D 数据表(PDF) 14 Page - NXP Semiconductors

APR2/D 数据表(HTML) 14 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载

链接网址

APR2/D 数据表(PDF) 14 Page - NXP Semiconductors

APR2/D 数据表(HTML) 14 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表 下载

链接网址

数据表下载