APR2SLASHD datasheet(28/101 Pages) NXP

28 / 101 page

2-10

DSP56001A/D, Rev. 1

MOTOROLA

DSP56001A

RESET, Stop, Mode Select, and Interrupt Timing

28 Delay from Level-Sensitive

IRQA Assertion to Fetch of First

Interrupt Instruction (when

exiting ‘Stop’)

(See Note 1)

•

Internal Crystal

Oscillator Clock, OMR

Bit 6 = 0

•

Stable External Clock,

OMR Bit 6 = 1

65548

× T

—

65548

× T

—

Note:

A clock stabilization delay is required when using the on-chip crystal oscillator in two cases:

• after power-on reset, and

• when recovering from Stop mode.

During this stabilization period, TC, TH, and TL will not be constant. Since this stabilization period

varies, a delay of 75,000

× T

C is typically allowed to assure that the oscillator is stable before

executing programs.

While it is possible to set OMR Bit 6 = 1 when using the internal crystal oscillator, it is not

recommended and these specifications do not guaraantee timings for that case.

Circuit stabilization delay is required during reset when using an external clock in two cases:

• after power-on reset, and

• when recovering from Stop mode.

When using fast interrupts and IRQA and IRQB are defined as level-sensitive, then timings 19

through 22 apply to prevent multiple interrupt service. To avoid these timing restrictions, the

deasserted Edge-Triggered mode is recommended when using fast interrupt. Long interrupts are

recommended when using Level-Sensitive mode.

Table 2-8

Reset, Stop, Mode Select, and Interrupt Timing (27/33 MHz) (Continued)

Num

Characteristics

27 MHz

33 MHz

Unit

Min

Max

Min

Max

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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