APR2SLASHD datasheet(12/101 Pages) NXP

12 / 101 page

1-6

DSP56001A/D, Rev. 1

MOTOROLA

DSP56001A

Interrupt and Mode Control

INTERRUPT AND MODE CONTROL

Table 1-8

Interrupt and Mode Control Signals

Signal Name

Signal

Type

State

during

Reset

Signal Description

MODA

IRQA

Input

Mode Select A/External Interrupt Request A

—This input has two

functions:

to select the initial chip operating mode, and

after synchronization, to allow an external device to

request a DSP interrupt.

MODA is read and internally latched in the DSP on exit from

Reset. MODA and MODB select the initial chip operating mode.

After leaving the Reset state, the MODA signal changes to external

interrupt request IRQA. The chip operating mode can be changed

by software after reset. The IRQA input is a synchronized external

interrupt request that indicates that an external device is

requesting service. It may be programmed to be level-sensitive or

negative-edge-triggered. If level-sensitive triggering is selected, an

external pull up resistor is required for wired-OR operation. If the

processor is in the Stop state and IRQA is asserted, the processor

will exit the Stop state.

MODB

IRQB

Input

Mode Select B/External Interrupt Request B

—This input has two

functions:

to select the initial chip operating mode, and

after internal synchronization, to allow an external device

to request a DSP interrupt.

MODB is read and internally latched in the DSP on exit from

Reset. MODA and MODB select the initial chip operating mode.

After leaving the Reset state, the MODB signal changes to external

interrupt request IRQB. After reset, the chip operating mode can

be changed by software. The IRQB input is an external interrupt

request that indicates that an external device is requesting service.

It may be programmed to be level sensitive or negative-edge-

triggered. If level-sensitive triggering is selected, an external pull

up resistor is required for wired-OR operation.

RESET

Input

Reset

—This input is a direct hardware reset on the processor.

When RESET is asserted low, the DSP is initialized and placed in

the Reset state. A Schmitt trigger input is used for noise immunity.

When the RESET signal is deasserted, the initial chip operating

mode is latched from MODA and MODB. The internal reset signal

is deasserted synchronously with the internal clocks.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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