APR2SLASHD datasheet(27/101 Pages) NXP

27 / 101 page

DSP56001A

RESET, Stop, Mode Select, and Interrupt Timing

MOTOROLA

DSP56001A/D, Rev. 1

2-9

22 Delay from General-Purpose

Output Valid to Interrupt

Request Deassertion for Level-

Sensitive Fast Interrupts (See

Note 3)—If Second Interrupt

Instruction is:

•

Single Cycle

•

Two Cycles

—

TL – 46

× T

C +

TL – 46

—

TL – 37

× T

C +

TL – 37

23 Synchronous Interrupt Setup

Time from IRQA, IRQB

Assertion to the second CKOUT

transition

TC - 816TC - 6

24 Synchronous Interrupt Delay

Time from the second CKOUT

transition to the First External

Address Output Valid caused

by the First Instruction Fetch

after coming out of Wait State

× T

C +

TH + 6

× T

C +

TH + 23

× T

C +

TH + 5

× T

C +

TH + 19

25 Duration for IRQA Assertion to

Recover from Stop State

19—16—

26 Delay from IRQA Assertion to

Fetch of First Interrupt

Instruction (when exiting ‘Stop’)

(See Note 1)

•

Internal Crystal

Oscillator Clock, OMR

Bit 6 = 0

•

Stable External Clock,

OMR Bit 6 = 1

65548

× T

—

65548

× T

—

27 Duration of Level-Sensitive

IRQA Assertion to ensure

interrupt service (when exiting

‘Stop’) (See Note 1)

•

Internal Crystal

Oscillator Clock, OMR

Bit 6 = 0

•

Stable External Clock,

OMR Bit 6 = 1

65534

× T

C +

× T

+ TL

—

65534

× T

C +

× T

+ TL

—

Table 2-8

Reset, Stop, Mode Select, and Interrupt Timing (27/33 MHz) (Continued)

Num

Characteristics

27 MHz

33 MHz

Unit

Min

Max

Min

Max

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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