APR2SLASHD datasheet(36/101 Pages) NXP

36 / 101 page

2-18

DSP56001A/D, Rev. 1

MOTOROLA

DSP56001A

Serial Communication Interface (SCI) Timing

SERIAL COMMUNICATION INTERFACE (SCI) TIMING

VCC = 5.0 V ± 10% for 27 MHz; 5.0 V ± 5% for 33 MHz;

TJ =-40 to 105 ˚C; CL = 50 pF + 1 TTL loads

tSCC = Synchronous Clock Cycle Time (For internal clock, tSCC is determined by the SCI Clock

Control Register and TC.) The minimum tSCC value is 8 × TC.

Table 2-10

SCI Synchronous Mode Timing (27/33 MHz)

Num

Characteristics

27 MHz

33 MHz

Unit

Min

Max

Min

Max

Synchronous Clock Cycle—tSCC

× T

—8

× T

—ns

Clock Low Period

× T

C– 15

—

× T

C– 13

—

Clock High Period

× T

C– 15

—

× T

C– 13

—

< intentionally blank >

————

—

Output Data Setup to Clock

Falling Edge (Internal Clock)

× T

C + TL –

—2

× T

C + TL –

—ns

Output Data Hold After Clock

Rising Edge (Internal Clock)

× T

C – TL –

—2

× T

C – TL –

—ns

Input Data Setup Time Before

Clock

Rising Edge (Internal Clock)

× T

C + TL +

—2

× T

C + TL +

—ns

Input Data Not Valid Before

Clock Rising Edge (Internal

Clock)

—2

× T

C + TL –

—2

× T

C + TL –

Clock Falling Edge to Output

Data Valid (External Clock)

—48—39

Output Data Hold After Clock

Rising Edge (External Clock)

TC + 9

—

TC + 8

—

Input Data Setup Time Before

Clock

Rising Edge (External Clock)

23—19—

Input Data Hold Time After

Clock Rising Edge (External

Clock)

31—25—

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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