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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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APR2/D 数据表(PDF) 46 Page - NXP Semiconductors |
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APR2/D 数据表(HTML) 46 Page - NXP Semiconductors |
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46 / 101 page  2-28 DSP56001A/D, Rev. 1 MOTOROLA DSP56001A External Bus Asynchronous Timing 128 Input Data Hold Time to RD Deassertion 0—0— ns 129 RD Assertion Width • WS = 0 • WS > 0 TC - 7 (WS + 1) × T C - 7 — — TC - 5.5 (WS + 1) × T C - 5.5 — — ns ns 130 Address Valid to Input Data Valid • WS = 0 • WS > 0 — — TC + TL - 14 (WS + 1) × T C + TL - 14 — — TC + TL - 11 (WS + 1) × T C + TL - 11 ns ns 131 Address Valid to RD Assertion TL - 7 TL + 5 TL - 5.5 TL + 5 ns 132 RD Assertion to Input Data Valid • WS = 0 • WS > 0 — — TC - 11 (WS + 1) × T C - 11 — — TC - 9 (WS + 1) × T C - 9 ns ns 133 WR Deassertion to RD Assertion TC - 12 — TC - 10 — ns 134 RD Deassertion to RD Assertion TC - 8 — TC - 6.5 — ns 135 WR Deassertion to WR Assertion • WS = 0 • WS > 0 TC - 12 TC + TH - 12 — — TC - 10 TC + TH - 10 — — ns ns 136 RD Deassertion to WR Assertion • WS = 0 • WS > 0 TC - 8 TC + TH - 8 — — TC - 6.5 TC + TH - 6.5 — — ns ns Table 2-13 External Bus Asynchronous Timing (Continued) No. Characteristics 27 MHz 33 MHz Unit Min Max Min Max Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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