APR2SLASHD datasheet(32/101 Pages) NXP

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2-14

DSP56001A/D, Rev. 1

MOTOROLA

DSP56001A

Host I/O (HI) Timing

HOST I/O (HI) TIMING

VCC = 5.0 V ± 10% for 27 MHz; 5.0 V ± 5% for 33 MHz;

TJ =-40 to 105 ˚C; CL = 50 pF + 1 TTL loads

Note:

Active low lines should be pulled up in a manner consistent with the AC and

DC specifications.

Table 2-9

Host I/O Timing (27/33 MHz)

Num

Characteristics

27 MHz

33 MHz

Unit

Min

Max

Min

Max

30 Host Synchronization Delay

(see Note 1)

TC + TL

31 HEN/HACK Assertion Width

(See Note 2)

•

CVR, ICR, ISR, RXL

Read

•

IVR, RXH/M Read

•

Write

TC + 46

—

TC + 37

—

32 HEN/HACK Deassertion

Width (See Note 2)

•

Between Two TXL

Writes (See Note 3)

•

Between Two CVR,

ICR, ISR, RXL Reads

(See Note 4)

× T

C + 46

× T

C + 46

—

× T

C + 37

× T

C + 37

—

33 Host Data Input Setup Time

Before HEN/HACK

Deassertion

4—4—

34 Host Data Input Hold Time

After HEN/HACK Deassertion

4—4—

35 HEN/HACK Assertion to

Output Data Active from High

Impedance

0—0—

36 HEN/HACK Assertion to

Output Data Valid

—39—31

37 HEN/HACK Deassertion to

Output Data High Impedance

(See Note 6)

—27—22

38 Output Data Hold Time After

HEN/HACK Deassertion (See

Note 7)

4—4—

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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