APR2SLASHD datasheet(50/101 Pages) NXP

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2-32

DSP56001A/D, Rev. 1

MOTOROLA

DSP56001A

Bus Strobe / Wait Timing

BUS STROBE / WAIT TIMING

VCC = 5.0 V ± 10% for 27 MHz; VCC = 5.0 V ± 5% for 33 MHz;

TJ = –40 to 105˚ C; CL = 50 pF + 2 TTL loads

Table 2-15

Bus Strobe / Wait Timing

No.

Characteristics

27 MHz

33 MHz

Unit

Min

Max

Min

Max

150 First CKOUT transition to BS

Assertion

2.5

151 WT Assertion to first CKOUT

transition (setup time)

—

2.5

—

152 First CKOUT transition to WT

Deassertion for Minimum Timing

TC - 6

TC – 5

153 WT Deassertion to first CKOUT

transition for Maximum Timing

(2 wait states)

6—5—

154 Second CKOUT transition to

BS Deassertion

320319

155 BS Assertion to Address Valid

-2

6.5

156 BS Assertion to WT Assertion

(See Note 1)

0TC - 11

TC – 10

157 BS Assertion to WT Deassertion

(See Note 1 and Note 3)

•

WS < 2

•

WS > 2

(WS - 1)

× T

C – 11

× T

C - 11

TC + 4

(WS - 1)

× T

+ 4

2 × T

C – 10

× T

C - 10

158 WT Deassertion to BS

Deassertion

TC + TL

× T

C + TL +

TC + TL

× T

C + TL +

159 Minimum BS Deassertion

Width for Consecutive

External Accesses

TH - 6

—

TH - 4.5

—

160 BS Deassertion to Address

Invalid (See Note 2)

TH - 8

TH - 6.5

—

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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