| 数据搜索系统,热门电子元器件搜索 |
|
APR2/D 数据表(PDF) 11 Page - NXP Semiconductors |
|
|
|||||||||||||||||||||||||||||
APR2/D 数据表(HTML) 11 Page - NXP Semiconductors |
|
11 / 101 page ![]() DSP56001A Bus Control MOTOROLA DSP56001A/D, Rev. 1 1-5 BUS CONTROL Table 1-7 Bus Control Signals Signal Name Signal Type State during Reset Signal Description PS Output Tri-stated Program Memory Select—PS is asserted low for external program memory access. PS is tri-stated when the BG or RESET signal is asserted. DS Output Tri-stated Data Memory Select—DS is asserted low for external data memory access. DS is tri-stated when the BG or RESET signal is asserted. X/Y Output Tri-stated X/Y External Memory Select—This output is driven low during external Y data memory accesses. It is also driven low during external exception vector fetches when operating in the Development mode. X/Y is tri-stated when the BG or RESET signal is asserted. BR WT Input/ Output Tri-stated Bus Request/Wait—The bus request input BR allows another device such as a processor or DMA controller to become master of the external data bus D0–D23 and external address bus a0–a15. When operating mode register (OMR) bit 7 is clear and BR is asserted, the DSP56001A will always release the external data bus D0–D23, address bus A0–A15, and bus control signals PS, DS, X/Y, RD, and WR (i.e. Port A), by tri-stating these pins after execution of the current instruction has been completed. If OMR bit 7 is set, this pin is an input that allows an external device to force wait states during an external Port A operation for as long as WT is asserted. Note: To prevent erroneous operation, pull up the BR/WT signal when it is not in use. BG BS Input/ Output Tri-stated Bus Grant/Bus Select—If OMR Bit 7 is clear, this output is asserted to acknowledge an external bus request after Port A has been released. If OMR Bit 7 is set, this signal is bus strobe, and is asserted when the DSP accesses Port A. WR Output Tri-stated Write Enable—WR is asserted during external memory write cycles. WR is tri-stated when the BG or RESET signal is asserted. RD Output Tri-stated Read Enable—RD is asserted during external memory read cycles. RD is tri-stated when the BG or RESET signal is asserted. Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |