APR2SLASHD datasheet(51/101 Pages) NXP

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DSP56001A

Bus Strobe / Wait Timing

MOTOROLA

DSP56001A/D, Rev. 1

2-33

161 Data-In Valid to RD

Deassertion (Set Up)

12—10—

Note:

If wait states are also inserted using the BCR and if the number of wait states is greater than two,

then specification numbers T156 and T157 can be increased accordingly.

BS deassertion to address invalid indicates the time after which the address are no longer

guaranteed to be valid.

The minimum number of wait states when using BS/WT is two (2).

For read-modify-write instructions, the address lines will not change states between the read and

the write cycle. However, BS will deassert before asserting again for the write cycle. If wait states

are desired for each of the read and write cycle, the WT pin must be asserted once for each cycle.

Figure 2-24 Asynchronous BS / WT Timings

Table 2-15

Bus Strobe / Wait Timing (Continued)

No.

Characteristics

27 MHz

33 MHz

Unit

Min

Max

Min

Max

Note:

During Read-Modify-Write instructions, the address lines do not change state.

However, BS will deassert before asserting again for the write cycle.

Data In

Data Out

A0–A15,

PS, DS,

X/Y

D0–D23

155

157

156

158

131

126

128

161

160

120

122

123

124

159

125

AA0398

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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