APR2SLASHD datasheet(80/101 Pages) NXP

80 / 101 page

4-6

DSP56001A/D, Rev. 1

MOTOROLA

DSP56001A

Electrical Design Considerations

ELECTRICAL DESIGN CONSIDERATIONS

Use the following list of recommendations to assure correct DSP operation:

•

Provide a low-impedance path from the board power supply to each VCC pin on the DSP,

and from the board ground to each GND pin.

•

Use at least four 0.1

µF bypass capacitors positioned as close as possible to the four sides

of the package to connect the VCC power source to GND.

•

Ensure that capacitor leads and associated printed circuit traces that connect to the chip

VCC and GND pins are less than 0.5 inch per capacitor lead.

•

Use at least a four-layer Printed Circuit Board (PCB) with two inner layers for VCC and

GND.

•

Because the DSP output signals have fast rise and fall times, PCB trace lengths should be

minimal. This recommendation particularly applies to the address and data buses as well

as the RD, WR, IRQA, IRQB, NMI, HEN, and HACK pins.

•

Consider all device loads, as well as parasitic capacitance due to PCB traces, when

calculating capacitance. This is especially critical in systems with higher capacitive loads

that could create higher transient currents in the VCC and GND circuits.

•

All inputs must be terminated (i.e., not allowed to float) using CMOS levels.

CAUTION

This device contains protective circuitry to

guard against damage due to high static

voltage or electrical fields. However, normal

precautions are advised to avoid application

of any voltages higher than maximum rated

voltages

this

high-impedance

circuit.

Reliability of operation is enhanced if unused

inputs are tied to an appropriate logic voltage

level (e.g., either GND or VCC).

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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