APR2SLASHD datasheet(82/101 Pages) NXP

82 / 101 page

4-8

DSP56001A/D, Rev. 1

MOTOROLA

DSP56001A

Host Port Considerations

Host Programming Considerations

UNSYNCHRONIZED READING OF RECEIVE BYTE REGISTERS

When reading receive byte registers, RXH or RXL, the host program should use interrupts or poll

the RXDF flag, which indicates that data is available. This assures that the data in the receive

byte registers will be stable.

OVERWRITING TRANSMIT BYTE REGISTERS

The host program should not write to the transmit byte registers, TXH or TXL, unless the TXDE

bit is set, indicating that the transmit byte registers are empty. This guarantees that the transmit

byte registers will transfer valid data to the HRX register.

SYNCHRONIZATION OF STATUS BITS FROM DSP TO HOST

HC, HREQ, DMA, HF3, HF2, TRDY, TXDE, and RXDF status bits are set or cleared from inside

the DSP and read by the host processor (refer to the User’s Manual for descriptions of these status

bits). The host can read these status bits very quickly without regard to the clock rate used by the

DSP, but the state of the bit could be changing during the read operation. Generally, this is not a

system problem, since the bit will be read correctly in the next pass of any host polling routine.

However, if the host asserts HEN for more than timing number 31, with a minimum cycle time

of timing number 31 + 32, then these status bits are guaranteed to be stable. Exercise care when

reading status bits HF3 and HF2 as an encoded pair. If the DSP changes HF3 and HF2 from 00

to 11, there is a small probability that the host could read the bits during the transition and

receive 01 or 10 instead of 11. If the combination of HF3 and HF2 has significance, the host

could read the wrong combination. Therefore, read the bits twice and check for consensus.

OVERWRITING THE HOST VECTOR

The host program should change the Host Vector register only when the Host Command bit

(HC) is clear. This change will guarantee that the DSP interrupt control logic will receive a stable

vector.

CANCELLING A PENDING HOST COMMAND EXCEPTION

The host processor may elect to clear the HC bit to cancel the host command exception request at

any time before it is recognized by the DSP. Because the host does not know exactly when the

exception will be recognized (due to exception processing synchronization and pipeline delays),

the DSP may execute the host command exception after the HC bit is cleared. For these reasons,

the HV bits must not be changed at the same time that the HC bit is cleared.

VARIANCE IN THE HOST INTERFACE TIMING

The Host Interface (HI) may vary. Therefore, a host which attempts to load (bootstrap) the DSP

should first make sure that the part has completed its HI port programming (e.g., by setting the

INIT bit in ICR then polling it and waiting it to be cleared, then reading the ISR or by writing the

TREQ/RREQ together with the INIT and then polling INIT, ISR, and the HREQ pin).

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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