APR2SLASHD datasheet(44/101 Pages) NXP

44 / 101 page

2-26

DSP56001A/D, Rev. 1

MOTOROLA

DSP56001A

External Bus Asynchronous Timing

EXTERNAL BUS ASYNCHRONOUS TIMING

VCC = 5.0 V ± 10% for 27 MHz;VCC = 5.0 V ± 5% for 33 MHz;

TJ = –40 to 105 ˚C; CL = 50 pF + 1 TTL loads

WS = Number of Wait States, as determined by BCR (WS = 0 to 15)

Capacitance Derating:

The DSP56001A external bus timing specifications are designed and

tested at the maximum capacitive load of 50 pF, including stray capacitance. Typically, the drive

capability of the external bus pins (A0-A15, D0-D23, PS, DS, RD, WR, X/Y) derates linearly at 1 ns

per 12 pF of additional capacitance from 50 pF to 250 pF of loading. Port B and C pins (HI, SCI,

SSI) derate linearly at 1 ns per 5 pF of additional capacitance from 50 pF to 250 pF of loading.

Active low lines should be pulled up in a manner consistent with the AC and DC specifications.

Table 2-13

External Bus Asynchronous Timing

No.

Characteristics

27 MHz

33 MHz

Unit

Min

Max

Min

Max

115 Delay from BR Assertion to BG

Assertion

•

With no external access

from the DSP

•

During external read or

write access

•

During external read-

modify-write access

•

During Stop mode—

external bus will not be

released and BG will

not go low

•

During Wait mode

× T

C + TH

TC + TH

—

TH + 3

× T

C +

TH + 15

× T

C + TH +

TC × WS + 15

× T

C + TH +

× T

C × WS +

—

TC + TH + 23

× T

C + TH

TC + TH

—

TH + 3

× T

C +

TH + 13

× T

C + TH +

TC × WS + 13

× T

C + TH +

× T

C × WS +

—

TC + TH + 19

116 Delay from BR Deassertion to

BG Deassertion

× T

C + 15

× T

C + 13

117 BG Deassertion Duration

× T

C + TH –

—2

× T

C + TH –

—ns

118 Delay from Address, Data, and

Control Bus High Impedance to

BG Assertion

0—0—

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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