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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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APR2/D 数据表(PDF) 37 Page - NXP Semiconductors |
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APR2/D 数据表(HTML) 37 Page - NXP Semiconductors |
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37 / 101 page  DSP56001A Serial Communication Interface (SCI) Timing MOTOROLA DSP56001A/D, Rev. 1 2-19 Table 2-11 SCI Asynchronous Mode Timing — 1X Clock Num Characteristics 27 MHz 33 MHz Unit Min Max Min Max 67 Asynchronous Clock Cycle— tACC 64 × T C — 64 × T C —ns 68 Clock Low Period 32 × T C – 15 — 32 × T C – 13 — ns 69 Clock High Period 32 × T C – 15 — 32 × T C – 13 — ns 70 < intentionally blank > ———— — 71 Output Data Setup to Clock Rising Edge (Internal Clock) 32 × T C – 77 — 32 × T C – 61 — ns 72 Output Data Hold After Clock Rising Edge (Internal Clock) 32 × T C – 77 — 32 × T C – 61 — ns Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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