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APR2/D 数据表(PDF) 45 Page - NXP Semiconductors |
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APR2/D 数据表(HTML) 45 Page - NXP Semiconductors |
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45 / 101 page  DSP56001A External Bus Asynchronous Timing MOTOROLA DSP56001A/D, Rev. 1 2-27 119 Delay from BG Deassertion to Address and Control Bus Enabled 0TH-80TH-6 ns 120 Address Valid to WR Assertion • WS = 0 • WS > 0 TL - 7 TC - 7 TL + 5 TC + 5 TL - 5.5 TC - 5.5 TL + 5 TC + 5 ns ns 121 WR Assertion Width • WS = 0 • WS > 0 TC - 7 WS × T C + TL - 7 — — TC - 5 WS × T C + TL - 5 — — ns ns 122 WR Deassertion to Address Not Valid TH - 9 — TH - 7.5 — ns 123 WR Assertion to Data Out Active From High Impedance • WS = 0 • WS > 0 TH - 7 0 TH + 8 8 TH - 5.5 0 TH + 6.5 6.5 ns ns 124 Data Out Hold Time from WR Deassertion (the maximum specification is periodically sampled, and not 100% tested) TH - 7 TH + 6 TH - 5.5 TH + 4.5 ns 125 Data Out Setup Time to WR Deassertion • WS = 0 • WS > 0 TL - 5 WS × T C + TL - 5 — — TL - 5 WS × T C + TL - 5 — — ns ns 126 RD Deassertion to Address Not Valid TH - 7 — TH - 5.5 — ns 127 Address Valid to RD Deassertion • WS = 0 • WS > 0 TC + TL - 6 (WS + 1) × T C + TL - 6 — — TC + TL - 6 (WS + 1) × T C + TL - 6 — — ns ns Table 2-13 External Bus Asynchronous Timing (Continued) No. Characteristics 27 MHz 33 MHz Unit Min Max Min Max Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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