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APR2/D 数据表(PDF) 8 Page - NXP Semiconductors |
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APR2/D 数据表(HTML) 8 Page - NXP Semiconductors |
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8 / 101 page ![]() 1-2 DSP56001A/D, Rev. 1 MOTOROLA DSP56001A Introduction Figure 1-1 Signals Identified by Functional Group DSP56001A 24 16 External Address Bus External Data Bus External Bus Control Synchronous Serial Interface (SSI) Port2 Clock Power Inputs: Clock Output Internal Logic Address Bus Data Bus Bus Control HI SSI/SCI A0–A15 D0–D23 PS DS X/Y BR/WT BG/BS RD WR EXTAL XTAL VCCCK VCCQ VCCA VCCD VCCC VCCH VCCS 4 Serial Communications Interface (SCI) Port2 3 2 3 Grounds: Clock Internal Logic Address Bus Data Bus Bus Control HI SSI/SCI GNDCK GNDQ GNDA GNDD GNDC GNDH GNDS 4 5 4 6 2 Interrupt/ Mode Control Reset Interrupt mode mode MODA IRQA MODB IRQB RESET Host Interface (HI) Port1 Host Port B Interface GPIO H0–H7 PB0–PB7 HA0–HA2 PB8–PB10 HR/W PB11 HEN PB12 HREQ PB13 HACK PB14 SCI Port Port C GPIO RXD PC0 TXD PC1 RCLK PC2 SSI Port Port C GPIO SC0–SC2 PC3–PC5 SCK PC6 SRD PC7 STD PC8 8 3 3 Note: 1. The Host Interface port signals are multiplexed with the Port B GPIO signals (PB0–PB15). 2. The SCI and SSI signals are multiplexed with the Port C GPIO signals (PC0–PC8). 3. Power and ground lines are indicated for the 144-pin TQFP package. AA0885 Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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