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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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APR2/D 数据表(PDF) 41 Page - NXP Semiconductors |
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APR2/D 数据表(HTML) 41 Page - NXP Semiconductors |
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41 / 101 page  DSP56001A Synchronous Serial Interface (SSI) Timing MOTOROLA DSP56001A/D, Rev. 1 2-23 102 FST Input (bl) Setup Time Before TXC Falling Edge 12 27 — 10 23 — x ck i ck ns ns 103 FST Input (wl) to Data Out Enable from High Impedance —46—37 ns 104 FST Input (wl) Setup Time Before TXC Falling Edge 15 42 — — 13 34 — — x ck i ck ns ns 105 FST Input Hold Time After TXC Falling Edge 27 4 — — 22 4 — — x ck i ck ns ns 106 Flag Output Valid After TXC Rising Edge — — 54 31 — — 43 25 x ck i ck ns ns Note: 1. For internal clock, External Clock Cycle is defined by Icyc and SSI control register. 2. Periodically sampled and not 100% tested Table 2-12 SSI Timing (Continued) Num Characteristics 27 MHz 33 MHz Case Unit Min Max Min Max Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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