APR2SLASHD datasheet(25/101 Pages) NXP

25 / 101 page

DSP56001A

RESET, Stop, Mode Select, and Interrupt Timing

MOTOROLA

DSP56001A/D, Rev. 1

2-7

RESET, STOP, MODE SELECT, AND INTERRUPT TIMING

VCC = 5.0 V ± 10% for 27 MHz; VCC = 5.0 V ± 5% for 33 MHz

TJ = -40 to +105 ˚C; CL = 50 pF + 1 TTL loads

WS = number of wait states programmed into the external bus access using BCR (WS = 0–15)

Table 2-8

Reset, Stop, Mode Select, and Interrupt Timing (27/33 MHz)

Num

Characteristics

27 MHz

33 MHz

Unit

Min

Max

Min

Max

Delay from RESET Assertion to

Address High Impedance

(periodically sampled and not

100% tested)

—38—31

10 Minimum Stabilization

Duration

•

Internal Oscillator (See

Note 1)

•

External clock (See

Note 2)

75000

× T

—

75000

× T

—

11 Delay from Asynchronous

RESET Deassertion to First

External Address Output

(Internal Reset Deassertion)

× T

C + 31

× T

C + 25

12 Synchronous Reset Setup Time

from RESET Deassertion to first

CKOUT transition

TC - 8

TC - 7

13 Synchronous Reset Delay Time

from the first CKOUT

transition to the First External

Address Output

× T

C + 5

× T

C + 23

× T

C + 5

× T

C + 19

14 Mode Select Setup Time

—

15 Mode Select Hold Time

0—0—

16 Minimum Edge-Triggered

Interrupt Request Assertion

Width

17—16—

16a Minimum Edge-Triggered

Interrupt Request Deassertion

Width

10—10—

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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