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APR2/D 数据表(PDF) 78 Page - NXP Semiconductors |
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APR2/D 数据表(HTML) 78 Page - NXP Semiconductors |
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78 / 101 page  4-4 DSP56001A/D, Rev. 1 MOTOROLA DSP56001A Substituting the DSP56001A for the DSP56001 CONTROL REGISTERS The OMR and the Status Register on the DSP56001A have been altered from those on the DSP56001. Refer to Table 4-2 for details of these alterations. HOST COMMAND VECTOR REGISTER The DSP56001A’s Host Command Vector Register (CVR) also differs from that of the DSP56001 (see Table 4-3). Table 4-2 Summary of Control Register Differences REGISTER BIT DSP56001 DEFINITION DSP56001A DEFINITION EXPLAINATION OF DIFFERENCE Status Register 7 Reserved— Read/Written as zero. Reserved— Read as don’t care. On the 001A this bit may be read as 0 or 1. The user should not rely on this bit being a given value. 14 Reserved— Read/Written as zero. Reserved— Write as zero only, read as don’t care. If this bit is set on the 56001A, the operations performed by the Data ALU change, and 56001 code will yield erroneous results. Write this bit only as zero. Operating Mode Register 3 Reserved— Read/.Written as zero Reserved— Write as zero only, read as don’t care. If this bit is set, memory reads may be from incorrect locations. Write this bit only as zero. Port B Control Register 1 Reserved— Written as zero. Reserved— Written as zero. Writing this bit as a 1 will result in behavior differences between the 001 and the 001A. Table 4-3 Summary of Host Command Vector Register Differences REGISTER BIT DSP56001 DEFINITION DSP56001A DEFINITION EXPLAINATION OF DIFFERENCE Host Command Vector Register (CVR) 5 Reserved— Read as zero. Reserved—Read as don’t care. This bit should be written with only a zero on the 56001A. Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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