APR2SLASHD datasheet(10/101 Pages) NXP

10 / 101 page

1-4

DSP56001A/D, Rev. 1

MOTOROLA

DSP56001A

Clock

CLOCK

ADDRESS BUS

DATA BUS

Table 1-4

Clock Signals

Signal

Name

Signal

Type

State

during

Reset

Signal Description

EXTAL

Input

External Clock/Crystal Input

—This input should be connected to an

external crystal or to an external oscillator.

XTAL

Output

Chip-

driven

Crystal Output

—This output connects the internal crystal oscillator

output to an external crystal. If an external oscillator is used, XTAL

should be left unconnected.

Table 1-5

Address Bus Signals

Signal

Names

Signal

Type

State

during

Reset

Signal Description

A0–A15

Output

Tri-

stated

Address Bus

—These signals specify the address for external

program and data memory accesses. If there is no external bus

activity, A0–A15 remain at their previous values to reduce power

consumption. A0–A15 are tri-stated when the bus grant signal is

asserted.

Table 1-6

Data Bus Signals

Signal

Names

Signal

Type

State

during

Reset

Signal Description

D0–D23

Input/

Output

Tri-

stated

Data Bus

—These signals provide the bidirectional data bus for

external program and data memory accesses. D0–D23 are tri-stated

when the BG or RESET signal is asserted.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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