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APR2/D 数据表(PDF) 43 Page - NXP Semiconductors |
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APR2/D 数据表(HTML) 43 Page - NXP Semiconductors |
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43 / 101 page ![]() DSP56001A Synchronous Serial Interface (SSI) Timing MOTOROLA DSP56001A/D, Rev. 1 2-25 Figure 2-20 SSI Receiver Timing Last Bit See Note Note: In the Network mode, output flag transitions can occur at the start of each time slot within the frame. In the Normal mode, the output flag state is asserted for the entire frame period. First Bit 80 82 84 86 87 89 88 92 90 92 93 81 91 94 SRD (Input/Output) FSR (Bit) Out FSR (Word) Out Data Out FSR (Bit) In FSR (Word) In Flags Out 85 AA0895 Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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