ADE5166 datasheet(122/148 Pages) AD

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ADE5166/ADE5169/ADE5566/ADE5569

Preliminary Technical Data

Rev. PrB | Page 122 of 148

Table 135. Serial Port Buffer SFR (SBUF, 0x99)

Bit

Mnemonic

Default

Description

7 to 0

SBUF

Serial Port Data Buffer.

Table 136. Enhanced Serial Baud Rate Control SFR (SBAUDT, 0x9E)

Bit

Mnemonic

Default

Description

OWE

Overwrite error. This bit is set when new data is received and RI = 1. It indicates that SBUF was not

read before the next character was transferred in, causing the prior SBUF data to be lost. Write a 0 to

this bit to clear it.

Frame error. This bit is set when the received frame does not have a valid stop bit. This bit is read

only and updated every time a frame is received.

Break error. This bit is set whenever the receive data line (Rx) is low for longer than a full transmission

frame, which is the time required for a start bit, eight data bits, a parity bit, and half a stop bit. This

bit is updated every time a frame is received.

4, 3

SBTH1, SBTH0

Extended divider ratio for baud rate setting as shown in Table 138.

2, 1, 0

DIV2, DIV1, DIV0

Binary divider. See Table 138.

DIV[2:0]

Result

000

Divide by 1.

001

Divide by 2.

010

Divide by 4.

011

Divide by 8.

100

Divide by 16.

101

Divide by 32.

110

Divide by 64.

111

Divide by 128.

Table 137. UART Timer Fractional Divider SFR (SBAUDF, 0x9D)

Bit

Mnemonic

Default

Description

UARTBAUDEN

UART baud rate enable. Set to enable UART timer to generate the baud rate.

When set, PCON.7 (SMOD), T2CON.4 (TCLK), and T2CON.5 (RCLK) are ignored.

Cleared to let the baud rate be generated as per a standard 8052.

Not Implemented, write don’t care.

SBAUDF.5

UART Timer Fractional Divider Bit 5.

SBAUDF.4

UART Timer Fractional Divider Bit 4.

SBAUDF.3

UART Timer Fractional Divider Bit 3.

SBAUDF.2

UART Timer Fractional Divider Bit 2.

SBAUDF.1

UART Timer Fractional Divider Bit 1.

SBAUDF.0

UART Timer Fractional Divider Bit 0.

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