ADE5166 datasheet(118/148 Pages) AD

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ADE5166/ADE5169/ADE5566/ADE5569

Preliminary Technical Data

Rev. PrB | Page 118 of 148

Table 131. Leap Years—Rollover After 29 Days

Year Register

Estimated Year

0d04

2004

0d08

2008

0d12

2012

0d16

2016

0d20

2020

0d24

2024

0d28

2028

0d32

2032

0d36

2036

0d40

2040

0d44

2044

0d48

2048

0d52

2052

0d56

2056

0d60

2060

0d64

2064

0d68

2068

0d72

2072

0d76

2076

0d80

2080

0d84

2084

0d88

2088

0d96

2092

0d96

2096

RTC INTERRUPTS

The RTC alarm and interval timer interrupts are enabled by

setting the ETI bit in the interrupt enable and Priority 2 SFR

(IEIP2, 0xA9). When an alarm or Interval Timer event occurs,

the corresponding flag is set and a pending RTC interrupt is

generated. If the RTC interrupt is enabled, the program vectors

to the RTC interrupt address and the corresponding RTC flag

can be cleared in software. Moving to the RTC interrupt address

alone does not automatically clear the flag. To successfully

acknowledge the interrupt event, the flag has to be cleared by

software. If the RTC interrupt is disabled when the event

occurs, the pending interrupt remains until the corresponding

RTC flag is cleared. The ALFLAG and ITFLAG flags therefore

drive the RTC interrupt, and should be managed by the user to

keep track of the RTC events.

Note that if the ADE5166/ADE5169/ADE5566/ADE5569 are

awakened by an RTC event, either the ALFLAG or ITFLAG,

then the pending RTC interrupt must be serviced before the

ADE5166/ADE5169/ADE5566/ADE5569 can go back to sleep

again. The ADE5166/ADE5169/ADE5566/ADE5569 keep

waking up until this interrupt has been serviced.

Interval Timer Alarm

The RTC can be used as an interval timer. When the interval

timer is enabled by setting the ITEN bit in the RTC configuration

SFR (TIMECON, 0xA1), the interval timer clock source selected

by the ITS1 and ITS0 bits is passed through to an 8-bit counter.

This counter increments on every interval timer clock pulse

until the 8-bit counter is equal to the value in the alarm interval

and creating a pending RTC interrupt. If the SIT bit in the RTC

configuration SFR (TIMECON, 0xA1) is clear, the 8-bit counter

is cleared and starts counting again. If the SIT bit is set then the

8-bit counter is held in reset after the alarm occurs.

Take care when changing the interval timer timebase. The

recommended procedure is as follows:

If the INTVAL register is going to be modified, write this

synchronize with the RTC, 64,000 cycles at a 4.096 MHz

instruction cycle clock.

Disable the interval timer by clearing the ITEN bit in the

TIMECON SFR. Then wait for one 128 Hz clock cycle to

synchronize with the RTC, 64,000 cycles at a 4.096 MHz

instruction cycle clock.

Read the TIMECON SFR to ensure that the ITEN bit is

clear. If it is not, wait for another 128 Hz clock cycle.

Set the timebase bits, ITS[1:0] in the TIMECON SFR to

configure the interval. Wait for a 128 Hz clock cycle for this

change to take effect.

Alarm

The RTC can be used with an alarm to wake up periodically.

The alarm registers (AL_SEC, AL_MIN, AL_HOUR, AL_DAY,

and AL_DATE) should be set to the specific time that the alarm

event is required, and the corresponding Alxx_EN bits set in the

TIMECON2 SFR (0xA2). The enabled alarm registers are then

compared to their respective RTC registers (SEC, MIN, HOUR,

DAY, and DATE) and when all enabled alarms match their

corresponding RTC registers, the alarm flag is set and a pending

interrupt is generated. The alarm flag is located in Bit 6 of the

TIMECON2 SFR (0xA2). If enabled, an RTC interrupt occurs

and the program vectors to the RTC interrupt address.

ADE5166 数据表(PDF) 118 Page - Analog Devices

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