ADE5166 datasheet(132/148 Pages) AD

132 / 148 page

ADE5166/ADE5169/ADE5566/ADE5569

Preliminary Technical Data

Rev. PrB | Page 132 of 148

SERIAL PERIPHERAL INTERFACE (SPI)

The ADE5166/ADE5169/ADE5566/ADE5569 integrate a

complete hardware serial peripheral interface on-chip. The SPI

is full duplex so that eight bits of data are synchronously transmit-

ted and simultaneously received. This SPI implementation is

double buffered, allowing users to read the last byte of received

data while a new byte is shifted in. The next byte to be transmitted

can be loaded while the current byte is shifted out.

The SPI port can be configured for master or slave operation.

The physical interface to the SPI is via the MISO (P0.5),

MOSI (P0.4), SCLK (P0.6), and SS (P0.7) pins, while the

firmware interface is via the SPI Configuration SFR 1

(SPIMOD1, 0xE8), the SPI Configuration SFR 2 (SPIMOD2,

0xE9), the SPI interrupt status SFR (SPISTAT, 0xEA), the

SPI/I2C transmit buffer SFR (SPI2CTx, 0x9A), and the SPI/I2C

receive buffer SFR (SPI2CRx, 0x9B).

Note that the SPI pins are shared with the I2C pins. Therefore, the

user can enable only one interface at a time. The SCPS bit in the

configuration SFR (CFG, 0xAF) selects which peripheral is active.

SPI REGISTERS

Table 144. SPI SFR List

SFR Address

Mnemonic

R/W

Length (Bits)

Default

Description

0x9A

SPI2CTx

SPI/I2C transmit buffer (see Table 145).

0x9B

SPI2CRx

SPI/I2C receive buffer (see Table 146).

0xE8

SPIMOD1

R/W

0x10

SPI Configuration SFR 1 (see Table 147).

0xE9

SPIMOD2

R/W

SPI Configuration SFR 2 (see Table 148).

0xEA

SPISTAT

R/W

SPI interrupt status (see Table 149).

Table 145. SPI/I2C Transmit Buffer SFR (SPI2CTx, 0x9A)

Bit

Mnemonic

Default

Description

7 to 0

SPI2CTx

SPI or I2C transmit buffer. When the SPI2CTx SFR is written, its content is transferred to the transmit

FIFO input. When a write is requested, the FIFO output is sent on the SPI or I2C bus.

Table 146. SPI/I2C Receive Buffer SFR (SPI2CRx, 0x9B)

Bit

Mnemonic

Default

Description

7 to 0

SPI2CRx

SPI or I2C receive buffer. When SPI2CRx SFR is read, one byte from the receive FIFO output is

transferred to the SPI2CRx SFR. A new data byte from the SPI or I2C bus is written to the FIFO input.

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