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ADE5166 数据表(PDF) 128 Page - Analog Devices |
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ADE5166 数据表(HTML) 128 Page - Analog Devices |
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128 / 148 page  ADE5166/ADE5169/ADE5566/ADE5569 Preliminary Technical Data Rev. PrB | Page 128 of 148 UART2 SERIAL INTERFACE The ADE5166/ADE5169/ADE5566/ADE5569 UART2 is an 8- bit or 9-bit UART with variable baud rate Variable baud rates are defined by using an internal timer to generate any rate between 300 bauds/s and 115,200 bauds/s. The UART2 serial interface provided in the ADE5166/ADE5169/ ADE5566/ADE5569 is a full-duplex serial interface. It is also receive buffered, by storing the first received byte in a receive buffer until the reception of the second byte is complete. The physical interface to the UART is provided via the RxD2 (P0.7/SS/T1) and TxD2 (P2.3/SDEN) pins, whereas the firmware interface is through the SFRs presented in Table 139. Both the serial port receive and transmit registers are accessed through the SBUF2 SFR (0xEB). Writing to SBUF2 loads the transmit register, and reading SBUF2 accesses a physically separate receive register. An enhanced UART mode is offered by using the UART timer and providing enhanced frame error, break error, and overwrite error detection. The SBAUD2 SFR is used to configure the UART2 timer and to indicate the enhanced UART2 errors. UART SFR REGISTER LIST Table 139. Serial Port 2 SFRs SFR Address Bit Addressable Description SCON2 0xE1 No Serial communications control (see Table 140) SBUF2 0xEB No Serial Port 2 buffer (see Table 141) SBAUD2 0xEE No Enhance serial baud rate control (see Table 142) Table 140. Serial Communications Control SFR (SCON2, 0xE1) Bit Mnemonic Default Description 7 N/A N/A Reserved 6 EN-T8 0 9-bit UART, variable baud rate enable bit. When set, the UART2 is in 9-bit mode. 5 OWE2 0 Overwrite error. This bit is set when new data is received and RI = 1. It indicates that SBUF2 was not read before the next character was transferred in, causing the prior SBUF2 data to be lost. Write a zero to this bit to clear it. 4 FE2 0 Frame error. This bit is set when the received frame does not have a valid stop bit. This bit is read only and updated every time a frame is received. 3 BE2 0 Break error. This bit is set whenever the receive data line (Rx2) is low for longer than a full transmission frame, the time required for a start bit, eight data bits, a parity bit, and half a stop bit. This bit is updated every time a frame is received. 2 REN2 0 Serial Port 2 receive enable bit. Set by user software to enable serial port reception. Cleared by user software to disable serial port reception. 1 TI2 0 Serial Port 2 transmit interrupt flag. Set by hardware at the end of the eighth bit, TI2 must be cleared by user software. 0 RI2 0 Serial Port 2 receive interrupt flag. Set by hardware at the end of the eighth bit, RI2 must be cleared by user software. Table 141. Serial port 2 Buffer SFR (SBUF2, 0xEB) Bit Mnemonic Default Description 7 to 0 SBUF2 0 Serial Port 2 data buffer. Table 142. Enhanced Serial baud rate control 2 SFR (SBAUD2, 0xEE) Bit Mnemonic Default Description 7 TB8 0 Serial port transmit (Bit 9). The data loaded into TB8 is the ninth data bit transmitted in 9-bit mode. 6 RB8 0 Serial port receiver (Bit 9). The ninth data bit received in 9-bit mode is latched into RB8. For 8-bit Mode, the stop bit is latched into RB8. 5 SBF2 Fractional divider boolean: When set, SBAUDF2 = 0x2B when clear, SBAUDF2 = 0x07. 4 to 3 SBTH2.1, SBTH2.0 0 Extended divider ratio for baud rate setting as shown in Table 138. |
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