TUSB3200CPAH datasheet(33/93 Pages) TI

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2–17

The other interrupt sources are the eight USB in endpoints, the eight USB out endpoints, USB function reset, USB

function suspend, USB function resume, USB start-of-frame, USB pseudo start-of-frame, USB setup stage

transaction, USB setup stage transaction over-write, CODEC port interface transmit data register empty, CODEC port

interface receive data register full, I2C interface transmit data register empty, I2C interface receive data register full,

and the external interrupt input.

The interrupts for the USB in endpoints and USB out endpoints can not be masked. An interrupt for a particular

endpoint occurs at the end of a successful transaction to that endpoint. A status bit for each in and out endpoint also

exists. However, these status bits are read only, and therefore, these bits are intended to be used for diagnostic

purposes only. After a successful transaction to an endpoint, both the interrupt and status bit for an endpoint will be

asserted until the interrupt is cleared by the MCU.

The USB function reset, USB function suspend, USB function resume, USB start-of-frame, USB pseudo

start-of-frame, USB setup stage transaction, and USB setup stage transaction over-write interrupts can all be

masked. A status bit for each of these interrupts also exists. Refer to the USB interrupt mask register and the USB

status register for more details. Note that the status bits for these interrupts are read only. For these interrupts, both

the interrupt and status bit will be asserted until the interrupt is cleared by the MCU.

The CODEC port interface transmit data register empty, CODEC port interface receive data register full, I2C Interface

transmit data register empty, and I2C interface receive data register full interrupts can all be masked. A status bit for

each of these interrupts also exists. Note that the status bits for these interrupts are read only. However, for these

interrupts, the status bits are not cleared automatically when the interrupt is cleared by the MCU. Refer to the CODEC

port interface control/status register and the I2C interface control/status register for more details.

The external interrupt input (XINT) is also ORed together with the on-chip interrupt sources. An enable bit exists for

this interrupt in the global control register. This interrupt does not have a status bit.

2.2.12 DMA Controller

The TUSB3200 provides four DMA channels for transferring data between the USB endpoint buffers and the CODEC

port interface. The DMA channels are provided to support the streaming of data for USB isochronous endpoints only.

Each DMA channel can be programmed to service only one isochronous endpoint. The endpoint number and

direction are programmable using the DMA channel control register provided for each of the four DMA channels.

The CODEC port interface time slots to be serviced by a particular DMA channel must also be programmed. For

example, an AC’97 mode stereo speaker application would use time slots 3 and 4 for audio playback. Therefore, the

DMA channel being used to move the audio data to the CODEC port interface would need time slot assignment bits

3 and 4 set to a 1. Each DMA channel is capable of being programmed to transfer data for time slots 0 through 13

using the two DMA channel time slot assignment registers provided for each DMA channel.

The number of bytes to be transferred for each time slot is also programmable. The number of bytes used should

be set based on the desired audio data format.

2.2.13 CODEC Port Interface

The CODEC port interface is a configurable serial interface used to transfer data between the TUSB3200 IC and a

CODEC device. The serial protocol and formats supported include AC ’97 1.0, AC ’97 2.0 and several I2S modes.

In addition, a general purpose mode is provided that can be configured to various user defined serial interface

formats.

Configuration of the interface is accomplished using the four CODEC port interface configuration registers, which are

CPTCNF1, CPTCNF2, CPTCNF3, and CPTCNF4. Please refer to section A.5.4 for more details on these registers.

The serial interface is basically a time division multiplexed (TDM)

time slot based scheme. The basic serial format

is programmed by setting the number of time slots per CODEC frame and the number of serial clock cycles (or bits)

per time slot. The interface in all modes is bidirectional and full duplex. For some modes, both audio data and

command/status data are transferred via the serial interface. The source of the transmit data and destination of the

receive data for all audio data time slots is the USB endpoint data buffers. Transfer of the audio data packets to/from

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