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TUSB3200CPAH 数据表(PDF) 36 Page - Texas Instruments |
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TUSB3200CPAH 数据表(HTML) 36 Page - Texas Instruments |
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36 / 93 page  2–20 Secondary MCLKO CSCHNE CRESET CDATI CDATO CSCLK CSYNC AC97CLK CRESET SD_OUT SD_IN BIT_CLK SYNC AC97CLK CRESET SD_OUT SD_IN BIT_CLK SYNC AC’97 IC TUSB3200 AC97 or MC97 Primary Figure 2–3. Connection of the TUSB3200 to Multiple AC ’97 CODECs 2.2.13.3 Inter-IC Sound (I2S) Modes of Operation The TUSB3200 offers a total of four I2S modes of operation. However, the serial format is the same for all four of the I2S modes. The difference in the I2S modes is simply the number of serial data outputs and/or serial data inputs supported. For instance, in CODEC port interface mode 4, there are three serial data outputs (SDOUT1, SDOUT2, SDOUT3) and one serial data input (SDIN1). Hence, mode 4 can be used to connect the TUSB3200 device to a CODEC with three stereo DACs and one ADC for multichannel audio applications. Note however that not all of the serial data outputs and/or inputs must be used for any given mode. Table 2–5 shows the TUSB3200 CODEC terminal assignments and the respective signal names for each of the I2S modes. Table 2–5. Terminal Assignments for CODEC Port Interface I2S Modes TERMINAL I2S I2S I2S I2S NO. NAME MODE 4 MODE 5 MODE 6 MODE 7 35 CSYNC LRCK O LRCK O LRCK O LRCK O 34 CSCLK SCLK O SCLK O SCLK O SCLK O 36 CDATO SDOUT1 O SDOUT1 O SDOUT1 O SDOUT1 O 38 CDATI SDOUT2 O SDOUT2 O SDIN1 I SDOUT2 O 39 CRESET SDOUT3 O SDIN1 I SDIN2 I SDOUT3 O 40 CSCHNE SDIN1 I SDIN2 I SDIN3 I SDOUT4 O In all I2S modes, the CODEC port interface is configured as a bidirectional full duplex serial interface with two time slots per frame. The frame sync signal is the left/right clock (LRCK) signal. Time slot 0 is used for the left channel audio data and time slot 1 is used for the right channel audio data. Both time slots should be set to 32 serial clock (SCLK) cycles in length giving an SCLK-to-LRCK ratio of 64. The serial clock frequency is based on the audio sample rate and the CODEC master clock (MCLK) frequency. For example, when using an audio sample rate (FS) of 48 kHz and an MCLK frequency of 12.288 MHz (256xFS), the SCLK frequency should be set to 3.072 MHz (64xFS). Note that the CODEC frame sync, the audio sample rate (FS), and the LRCK are all synonymous. The LRCK signal has a 50% duty cycle. The LRCK signal is low for the left channel time slot and is high for the right channel time slot. In addition, the LRCK signal is synchronous to the falling edge of the SCLK. Serial data is shifted out on the falling edge of SCLK and shifted in on the rising edge of SCLK. There is a one SCLK cycle delay from the edge of the LRCK before the most significant bit of the data is shifted out for both the left channel and right channel. For the I2S modes of the CODEC port interface, there is a 24-bit transmit and 24-bit receive shift register for each SDOUT and SDIN signal, respectively. As a result, the interface can actually support 16-bit, 18-bit, 20-bit or 24-bit transfers. The interface will pad the unused bits automatically with zeros. |
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