TUSB3200CPAH datasheet(74/93 Pages) TI

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A–26

A.5.2.12DMA Channel 0 Control Register (DMACTL0 – Address FFE8h)

The DMA channel 0 control register is contains various control bits for DMA channel 0.

Bit

Mnemonic

DMAEN

WABEN

—

EPDIR

EPNUM2

EPNUM1

EPNUM0

Type

R/W

Default

BIT

MNEMONIC

NAME

DESCRIPTION

DMAEN

DMA enable

The DMA enable bit is set to a 1 by the MCU to enable this DMA channel. Before

enabling the DMA channel, all other DMA channel configuration bits should be set to

the desired value.

WABEN

Wrap-around buffer enable

The wrap-around buffer enable bit is used by the MCU to enable or disable the

wrap-around buffer operation. The wrap-around buffer operation can only be used

by isochronous out endpoints or isochronous in endpoints that are serviced by the

DMA channels. The wrap-around buffer operation is enabled or disabled separately

for each DMA channel. For a DMA channel, the MCU should set this bit to a 1 to

enable the wrap-around buffer operation and clear this bit to a 0 to disable the

wrap-around buffer operation. Both the DMA channel and UBM logic use this bit to

determine the required functionality.

—

Reserved

Reserved for future use

—

Reserved

Reserved for future use

EPDIR

USB endpoint direction

The USB endpoint direction bit controls the direction of data transfer by this DMA

channel. The MCU should set this bit to a 1 to configure this DMA channel to be used

for a USB in endpoint. The MCU should clear this bit to a 0 to configure this DMA

channel to be used for a USB out endpoint.

2:0

EPNUM(2:0)

USB endpoint number

The USB endpoint number bits are set by the MCU to define the USB endpoint

number supported by this DMA channel. Keep in mind that endpoint 0 is always

used for the control endpoint, which is serviced by the MCU and not a DMA channel.

001b = Endpoint 1,

010b = Endpoint 2,

…,

111b = Endpoint 7

A.5.3

Adaptive Clock Generator Registers

This section describes the memory-mapped registers used for the adaptive clock generator control and operation.

The ACG has a set of seven registers.

A.5.3.1 Adaptive Clock Generator Frequency Register (Byte 0) (ACGFRQ0 – Address FFE7h)

The adaptive clock generator frequency register (byte 0) contains the least significant byte of the 24-bit ACG

frequency value. The adaptive clock generator frequency registers, ACGFRQ0, ACGFRQ1, and ACGFRQ2, contain

the 24-bit value used to program the ACG frequency synthesizer. The 24-bit value of these three registers is used

to determine the CODEC master clock output (MCLKO) signal frequency. See section 2.2.8 for the operation details

of the adaptive clock generator including instructions for programming the 24-bit ACG frequency value.

Bit

Mnemonic

FRQ7

FRQ6

FRQ5

FRQ4

FRQ3

FRQ2

FRQ1

FRQ0

Type

R/W

Default

BIT

MNEMONIC

NAME

DESCRIPTION

7:0

FRQ(7:0)

ACG frequency

The ACG frequency bit values are set by the MCU to program the ACG frequency

synthesizer to obtain the desired CODEC master clock output (MCLKO) signal

frequency.

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