TUSB3200CPAH datasheet(79/93 Pages) TI

79 / 93 page

A–31

A.5.4.3 CODEC port interface configuration register 3 (CPTCNF2 – Address FFDEh)

The CODEC port interface configuration register 3 is used to store various control bits for the CODEC port interface

operation.

Bit

Mnemonic

DDLY

TRSEN

CSCLKP

CSYNCP

CSYNCL

BYOR

CSCLKD

CSYNCD

Type

R/W

Default

BIT

MNEMONIC

NAME

DESCRIPTION

DDLY

Data delay

The data delay bit is set to a 1 by the MCU to program a one CSCLK cycle delay of

the serial data output and input signals in reference to the leading edge of the

CSYNC signal. The MCU should clear this bit to a 0 for no delay between these

signals.

TRSEN

3-State enable

The 3-state enable bit is set to a 1 by the MCU to program the hardware to 3-state the

serial data output signal for the time slots during the audio frame that are not valid.

The MCU should clear this bit to a 0 to program the hardware to use zero-padding for

the serial data output signal for time slots during the audio frame that are not valid.

CSCLKP

CSCLK polarity

The CSCLK polarity bit is used by the MCU to program the clock edge used for the

CODEC port interface frame sync (CSYNC) output signal, CODEC port interface

serial data output (CDATO) signal and CODEC port interface serial data Input

(CDATI) signal. When this bit is set to a 1, the CSYNC signal will be generated with

the negative edge of the CODEC port interface serial clock (CSCLK) signal. Also,

when this bit is set to a 1, the CDATO signal will be generated with the negative edge

of the CSCLK signal and the CDATI signal will be sampled with the positive edge of

the CSCLK signal. When this bit is cleared to a 0, the CSYNC signal will be

generated with the positive edge of the CSCLK signal. Also, when this bit is cleared

to a 0, the CDATO signal will be generated with the positive edge of the CSCLK

signal and the CDATI signal will be sampled with the negative edge of the CSCLK

signal.

CSYNCP

CSYNC polarity

The CSYNC polarity bit is set to a 1 by the MCU to program the polarity of the

CODEC port interface frame sync (CSYNC) output signal to be active high. The

MCU should clear this bit to a 0 to program the polarity of the CSYNC output signal to

be active low.

CSYNCL

CSYNC length

The CSYNC length bit is set to a 1 by the MCU to program the length of the CODEC

port interface frame sync (CSYNC) output signal to be the same number of CSCLK

cycles as time slot 0. The MCU should clear this bit to a 0 to program the length of the

CSYNC output signal to be one CSCLK cycle.

BYOR

Byte order

The byte order bit is used by the MCU to program the byte order for the data moved

by the DMA between the USB endpoint buffer and the CODEC port interface. When

this bit is set to a 1, the byte order of each audio sample will be reversed when the

data is moved to/from the USB endpoint buffer. When this bit is cleared to a 0, the

byte order of the each audio sample will be unchanged.

CSCLKD

CSCLK direction

The CSCLK direction bit is set to a 1 by the MCU to program the direction of the

CODEC port interface serial clock (CSCLK) signal as an input to the TUSB3200

device. The MCU should clear this bit to a 0 to program the direction of the CSCLK

signal as an output from the TUSB3200 device.

CSYNCD

CSYNC direction

The CSYNC direction bit is set to a 1 by the MCU to program the direction of the

CODEC port interface frame sync (CSYNC) signal as an input to the TUSB3200

device. The MCU should clear this bit to a 0 to program the direction of the CSYNC

signal as an output from the TUSB3200 device.

TUSB3200CPAH 数据表(PDF) 79 Page - Texas Instruments

TUSB3200CPAH 数据表(HTML) 79 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93

数据表下载